A Guide to PC Hardware Maintenance and Repair

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Chapter 9 Examining the Expansion Bus
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Objectives

• To look at the evolution and development of the
  expansion bus
• To get an intimate view of system resources
• To see what makes up the expansion bus
• To learn how data moves over the expansion bus
• To learn to troubleshoot the expansion bus

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Why do we even NEED one?

• To allow users to customize computers
• To provide a uniform speed for peripheral devices
  that is independent of CPU speed
• To provide control of system resources over
  devices added after a computer is manufactured

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The Functions of the Expansion Bus

• It provides system control over resources used by
  peripheral devices
• It provides a uniform speed and convention for
  transferring data from peripheral devices to the
  CPU.
• It synchronizes the transfer of data between
  devices and the CPU.

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System Resources

• Interrupt Request (IRQ)
• I/O Address
• DMA Channel

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Interrupt Request

• Acts like the doorbell between the CPU and
  another device.
• The CPU must think that only one device owns any
  given IRQ (OS can micro-manage that function).
• A device cannot initiate an I/O process.
• If the device wants to send data to the CPU it
  lights up the IRQ wire.

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Input Output Address

• The BASE I/O ADDRESS acts as the virtual address
  for the device.
• Devices also own other I/O address ranges that
  act as repositories for data.
• No two devices can own an overlapping I/O address
  under any circumstances without a conflict.

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• When a device wants to initiate communication
  with the CPU it lights up the IRQ wire.
• The CPU says, Not now, Im busy.
• The device says, So am I. You know where the
  data will be when you need it.
• Device dumps data into one of the I/O ranges
• When the CPU is ready for that data, it copies
  the contents of that address range.

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Direct Memory Access

• Some devices can transmit and receive data to and
  from memory without CPU intervention.
• A Direct Memory Access (DMA) channel is a direct
  line between RAM and a DMA-capable device.

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DMA Devices

• Memory Refresh
• A floppy diskette drive
• A sound card
• If a parallel port is configured for Enhanced
  Capabilities Port (ECP), it must be configured
  for a DMA channel.

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The Rules of DMA

• There are four 8-bit DMA channels and four 16-bit
  DMA channels.
• No two devices can share a DMA channel.
• DMA channel 2 cascades to DMA 4. They are the
  same channel.
• Ultra DMA is NOT the same creature.

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COM and LPT Ports

• COM Ports assigned to Serial Ports
• COM ports are virtual, while Serial ports are
  physical.
• Either serial port can have any COM port assigned
  to it.
• LPT Ports assigned to Parallel Ports
• See the rules for Serial and COM ports.

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Universal Serial Bus

• USB 1.0
• Up to 127 devices on a chain
• Fully Plug n Play compliant
• 12Mb/s transfer rate shared among all installed
  devices
• USB 2.0
• Increases speed to 480Mb/s

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Firewire

• Technically a SCSI standard
• IEEE-1394 and Firewire are the same
• Supports up to 63 devices on a chain
• 400Mb/s transfer rate

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The Evolution of the Expansion Bus

• The PC Bus
• ISA
• MCA
• EISA
• VLB
• PCI
• AGP
• PCI-X

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The PC Bus

• Frequently called 8-bit ISA
• Used on the PC and the PC-XT
• Was never an industry standard
• 8-bit bus
• 20-bit address bus

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ISA

• Industry Standards Association
• ISA didnt apply uniform standards until it was a
  16-bit bus
• 16-bit bus
• 24-bit address bus
• Added extra connectors needed onto an extension
  to maintain compatibility

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Limitations of ISA

• Early ISA was only a 7.66Mhz bus (later modified
  for the 8.33Mhz bus that became the standard).
• 24-bit address bus limits memory access to the
  lower 16MB of RAM.

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Micro Channel Architecture (MCA)

• Proprietary bus designed by IBM
• 32-bit bus
• 32-bit address bus
• 12Mhz bus speed
• Introduced Bus Mastering
• Two bus mastering devices communicate directly
  without CPU intervention
• Licensing fees preventing it from being
  successful

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Enhanced ISA (EISA)

• Industry standard 32-bit architecture released to
  the public domain
• Retained 8.33Mhz bus speed for compatibility with
  ISA
• Two-tiered slot allowed either ISA or EISA
  devices to be installed in an EISA slot

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VESA Local Bus

• Video Electronics Standards Association
• 32-bit bus
• 32-bit address bus
• 33Mhz speed (shared)
• If a second device is installed, bus speed drops
  to 16Mhz
• A third device drops bus speed to 8Mhz

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Peripheral Components Interconnect

• 32-bit bus
• 32-bit address bus
• PCI 1.0 was a 33Mhz bus, while PCI 2.1defined
  66Mhz slots and 64-bit slots
• Developed by Intel, but now is managed by the PCI
  Special Interest Group (PCI-SIG)

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PCI and Plug n Play (PnP)

• PCI is designed to be PnP by default
• ISA and VESA Local Bus, by default, is NOT PnP,
  but can be designed to be so.
• PCI devices had an Extended Capabilities
  Identifier Chip
• Identifies the device
• Lists its resource capabilities

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PCI and IRQs

• PCI devices can utilize edge-triggered or
  level-triggered IRQs.
• Edge triggered IRQ is electrical and is triggered
  by voltage being applied to a contact.
• Level triggered is where the device selects which
  IRQ channel to light up.
• PCI Devices have 4 IRQ channels
• Any one of them can be configured for use

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Advanced Graphics Port (AGP)

• Only for graphics adapters
• 66Mhz bus speed
• 2x AGP moves 2 bits per clock cycle
• 4x AGP moves 4 bits per clock cycle
• 8x AGP moves 8 bits per clock cycle

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AGP-Pro

• Is not faster than standard AGP
• High-speed video chips and memory require more
  power and run hotter
• Fans are needed to cool chips and memory
• Therefore the slot must deliver more power to the
  device
• Pro-50 overlaps 1 PCI slot
• Pro-110 overlaps 2 PCI slots

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PCI-X

• 64-bit 133Mhz bus
• A PCI-X bus can support either 133Mhz device, 2
  66Mhz devices or 4 33Mhz devices.
• Multiple PCI-X busses can be chained together
  using PCI-PCI bridges.
• Slots are color-coded for speed.