Dynamic Fraction Control Bus: New SystemonChip Communication Architecture Design

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Dynamic Fraction Control Bus New System-on-Chip
Communication Architecture Design

• University of Louisiana at Lafayette
• Center for Advanced Computer Studies
• Nan Wang and M. A. Bayoumi

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Outline

• Introduction Motivation
• Existing On-chip Communication Architectures
• New Architecture Design
• Test results
• Conclusion

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Keywords

• PEs- Processing Elements
• OCA- On-chip Communication Architecture
• Master Components the Components that can
  initiate a communication transaction
• Slave Components the Components that can only
  respond to the communication request
• FCB Fraction Control Bus

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Introduction Motivation

• General SOC System

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Introduction Motivation

• Provides Reuse Environment
• -- Module reused, IP, open source code
• -- Architecture reused, on-chip bus
• -- Verification reused, IP cores, VCs

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Introduction Motivation

• Importance of Communication Architectures
• 1. Increasing system Complexity
• 2. Global Interconnects dominate performance/
  power/ reliability
• 3. Increasing Availability of configurable
  Communication IP, feasibility for OCA selection

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Introduction Motivation

• Communication Architecture design Issues
• -- Communication Topology
• system shared bus, hierarchical bus structure,
  ring, mesh, custom bus networks
• -- Communication Protocols
• static priority, TDMA, Round robin, token
  passing
• -- Mapping of System communication

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Outline

• Introduction Motivation
• Existing Bus-based On-chip Communication
  Architectures
• New Architecture Design
• Test results
• Conclusion

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Existing Communication Architectures

• Evaluation of the Communication Architectures
• -- Design Complexity, Delay
• -- Control over the bus bandwidth fraction
• -- Communication latencies

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Static Priority Based Shared Bus
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TDMA Based Shared Bus
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TDMA Based Shared Bus
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LotteryBus Communication Architecture
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Lottery manager for static LOTTERYBUS architecture
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Advantages of LotteryBus
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Outline

• Introduction Motivation
• Existing On-chip Communication Architectures
• Proposed New Architecture Design
• Test results
• Conclusion

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Proposed Communication Architecture Fraction
Control

• Every master core is assigned a bus access
  fraction, the higher the fraction, the higher the
  priority
• the bus access will be decided by the Fraction
  Control bus arbitration rules statically or
  dynamically

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Proposed Communication Architecture Fraction
Control
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2. Communication Protocol Design Fraction Control

• Static Fraction Control Bus the assigned
  fractions are fixed during execution
• Dynamic Fraction Control Bus
• -- If any of the master core starves for bus
  access, its assigned fraction will be
  increased, and the difference will be borrowed
  from higher priority master cores temporarily.
• -- The borrowed part will be returned to the
  original owner when the situation has been
  changed.

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Communication Protocol Design Fraction Control

• Input request1..4, / bus requests /
• fraction1..4 / masters
  fractions /
• t_finish1..4 / transactions finished/
• Output grant1..4 / bus grant signals
  /
• for i1 to 4 do /grant clear when task/
• if (t_finishi1) then granti0 / is
  finished/
• While (requestltgt0 and grant0)
• if (requesti1 or 2 or 4 or 8) /only one
  master/
• then granti1 /has bus
  request /
• else for i1 to 4 do
• if (no masters fractionlt assigned
  fraction)
• then granti1 /master i is
  the master
• with highest priority /
• else if(only master is fractionltassigned
  fraction)
• then granti1
• else granti1 /master i
  is the master
• with highest priority /

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2. Communication Protocol Design Fraction Bus

• Bus Arbitration Case 1
• When only one master core is asking for bus
  access, the bus will be granted directly, no
  calculations needed
• ( LotteryBus, however, will still perform the
  computationmultiplication, random number
  generation and comparison)

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2. Communication Protocol Design Fraction Bus

• Bus Arbitration Case 2
• When more than one master cores are asking for
  bus access, and no masters current bus fraction
  is lower than the assigned bus access fraction,
  the bus access is granted to the master with
  higher Priority( or with higher assigned Bus
  Access Fraction)

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2. Communication Protocol Design Fraction Bus

• Bus Arbitration Case 3
• When more than one master cores are asking for
  bus access, the bus will be granted to the master
  core with the current bus bandwidth fraction
  lower than the assigned bus access fraction (if
  more than one master satisfy this condition, bus
  access will be decided by their priority)

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Outline

• Introduction Motivation
• Existing On-chip Communication Architectures
• New Architecture Design
• Test results
• Conclusion

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Generic Test System

• We implemented the priority Bus, LotteryBus, SFCB
  and DFCB architectures, and map the architectures
  onto
• Xilinx Vertex2Pro FPGA. The targeting device is
  xc2vp2, package fg456.
• Modelsim SE 5.8C and Xilinx ISE

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Generic Test System
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Generic Test System

• Application 88 matrix multiplication
• -- every master core performs computation for two
  rows of the result matrix (18 reads of 8 words
  input data, 16 writes of two words output data
  and 168 word multiplications and 167 additions
  for every master core)

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Generic Test System

• Priority MC14, MC23,MC32, MC41 ( 1-4, High
  to low)
• Lottery MC11, MC21, MC34, MC46 ( 1146)
• Fraction MC18, MC28, MC332, MC452
  (1146.5)

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Design Complexity, Speed and Bandwidth Fraction
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Generic Test System

• Communication latencies (clock cycles/ per word,
  including waiting time and transfer time)

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ATM Switch Architecture
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ATM Switch Architecture

• (1) traffic through port 4 needs to pass through
  the switch with minimum latency, and
• (2) ports 1,2,3 must share the bandwidth in the
  ratio114.

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ATM Switch Architecture

• (1) static priority architecture, priorities were
  4,3,2,1
• (2) Lottery Bus, lottery numbers were 1146
• (3)(4) SFCB and DFCB, 15156010.

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ATM Switch Architecture
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Outline

• Introduction Motivation
• Existing On-chip Communication Architectures
• New Architecture Design
• Test results
• Conclusion

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Conclusion

• PriorityBad Bandwidth distribution control,
  significant communication latencies for lower
  priority components
• LotteryBus better bus bandwidth distribution
  control than Priority bus, (tickets ratio
  1146, result 11.534.2) with fair
  communication latencies

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Conclusion

• SFCBDFCB
• 1. Comparative bandwidth distribution
• 2. SFCB has better bus bandwidth control
  (assigned ratio 1146.5, result 113.85.8)
• 3. DFCB has more balanced bus bandwidth
  distribution which increases the usage of the
  system resources and the system efficiency.

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• Thank you!!