A new efficient approach to automated dualrail synthesis

1
Design of Asynchronous Circuits by Synchronous
CAD tools
Kelvin Lwin Reshape Inc.
Alex Kondratyev Cadence Berkeley Lab.
2
Outline

• Motivation
• Null Convention Logic
• Automatic design flow
• Experiments and conclusions

3
Motivation
Hard

• Performance
• Power consumption
• Low EMI
• Modularity, robustness, etc.

Free Lunch
Soft
4
What is Going Wrong?
5
What is Going Wrong?
Asynchronous
Synchronous
Unification of design flows and design tools
6
Related Work

• Null Convention Logic (NCL) (Fant96)

• Delay-insensitive encoding and synthesis
• (Armstrong69, Sparso93)

• Micropipelines (Sutherland89)

7
Introduction to NCL
2-phase functioning (evaluate (DATA) precharge
(NULL))
Self-timed register interaction (acknowledgement
of phases)
Reg.
Reg.
Combinational logic
CD
NULL
Micropipeline with delay-insensitive (DI) datapath
8
NCL Gates
NULL - DATA
28 gates (library up to 4 inputs)
Gates are 1. sequential 2. unate
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NCL Registers
g
x1
x2
C-latch
C-latches Compl. detector
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NCL Design Flow
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From 2 to 3-rail Scheme
Not DI scheme!!!
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From 2 to 3-rail Scheme
Rationale behind delay-insensitivity of 3-rail
scheme

• 2-rail circuit is hazard-free under monotonic
  input changes

• All inputs changes are observable at outputs

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NCLX flow (MUX )
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NCLX Optimization

• Separation of functionality from completeness
• provides a room for optimization through
• Logic
• completion part is a big AND tree
  (well-optimized)
• completion through functional part
• Timing
• - simplification by timing assumptions (checked
  by STA)
• Library
• - use of Boolean instead of NCL gates

15
Logic Optimization
Completion part is a big AND tree
well-optimized
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First Attempt. Pattern Matching
Sparso93
a.1
out.1
b.1
a
out
b
out.0
a.0
b.0
(delay-insensitive 2-rail implementation)
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MUX Example
Ligthart00
a
z
s
z
b
Very-very large!!!
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Experimental Results
For Boolean library should be much better!!!
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Conclusions
Asynchronous design could be

• Easy (supported by commercial tools)

• General (similar to synchronous RTL subset)

• Efficient (for niche applications)