Gigabit IP Routing on Raw

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Gigabit IP Routing on Raw

• Gleb Chuvpilo, David Wentzlaff,
• and Saman Amarasinghe
• Laboratory for Computer Science
• Massachusetts Institute of Technology

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Talk at a Glance

• Project goal
• Raw processor overview
• Router design
• Rotating crossbar algorithm
• Implementation and results
• Future work

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We are on...

• Project goal
• Raw processor overview
• Router design
• Rotating crossbar algorithm
• Implementation and results
• Future work

4
Project Goal

• Build a fast IP router on a
• general-purpose architecture
• WHY?
• Its flexible ? configure for changing protocols
  and services!
• Its cheap ? economies of scale!

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We are on...

• Project goal
• Raw processor overview
• Router design
• Rotating crossbar algorithm
• Implementation and results
• Future work

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Technology

• Good news miniaturization
• Smaller transistors
• Shorter clock cycles
• Bad news long wires
• High data propagation delays
• Low energy efficiency

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Also

• Need sufficient I/O bandwidth
• for data streams

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• Our Solution?

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The Raw Processor
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Raw Fast Facts

• 16 MIPS-like tiles on a single die
• 2 MB SRAM on-chip
• 1,080 signal I/O pins
• 201 Gbps of external chip bandwidth

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Plus

• Raw is easily scalable
• up to 1024 tiles!

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Raw Layout
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Communication Between Tiles

• Two identical static networks
• Two identical dynamic networks

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Static Networks

• Destinations known at compile time
• Message size known at compile time
• Cycle-by-cycle switch schedule
• Three cycle nearest neighbor send-to-use latency
• No processing overhead

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Static Network Illustrated
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Dynamic Networks

• Unpredictable events
• external asynchronous interrupts
• cache misses
• 15 to 30 cycle nearest neighbor send-to-use
  latency (message header processing overhead)

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We are on...

• Project goal
• Raw processor overview
• Router design
• Rotating crossbar algorithm
• Implementation and results
• Future work

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• Problem

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Given Four Networks...
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...and Sixteen Tiles
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Need

• Map semi-dynamic communication to a
  programmatically static interconnect

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• Solution?

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Take Four Tiles...
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Create Inputs...
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Take Four Tiles More...
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Create Outputs...
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Take Another Four Tiles...
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Create a Rotating Crossbar...
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Connect Inputs to Outputs...
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Take the Last Four Tiles...
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Create Route Lookup...
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Router!
Out1
Out2
In1
In2
In4
In3
Out4
Out3
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We are on...

• Project goal
• Raw processor overview
• Router design
• Rotating crossbar algorithm
• Implementation and results
• Future work

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Rotating Crossbar Algorithm

• Uses the static network
• create a set of possible switch configurations at
  compile time
• choose the necessary configuration at run-time,
  depending on incoming packets
• Similar to the Token Ring
• Token the right of a crossbar tile to connect
  its input to any output
• Master tile the tile with the token
• Slave tile other three tiles

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Rotating Crossbar Algorithm

• Uses the static network
• create a set of possible switch configurations at
  compile time
• choose the necessary configuration at run-time,
  depending on incoming packets
• Similar to the Token Ring
• Token the right of a crossbar tile to connect
  its input to any output
• Master tile the tile with the token
• Slave tile other three tiles

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Rotating Crossbar Illustrated
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Rotating Crossbar Illustrated
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Rotating Crossbar Illustrated
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Rotating Crossbar Illustrated
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Rotating Crossbar Illustrated
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Steps

• Main processor
• read headers
• choose configuration
• program the switch
• Switch processor
• read headers
• execute configuration

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Steps
Main
Switch
headers_request
headers
choose_config
config
route_body
confirm
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We are on...

• Project goal
• Raw processor overview
• Router design
• Rotating crossbar algorithm
• Implementation and results
• Future work

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Implementation

• Tested in the cycle-accurate simulator of the Raw
  processor
• Five configurations with differing internal
  packet sizes
• Route lookup is a switch/case statement
• Buffering is assumed to be on the input outside
  of the chip
• Raw prototype clock speed assumed to be 225 MHz

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Performance
Click (0.23)
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Analysis

• Performance is expected to grow 4 to 8 times with
  all static networks used
• Internal static network saturation is practically
  unreachable
• No hardware limitations have been encountered yet

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We are on...

• Project goal
• Raw processor overview
• Router design
• Rotating crossbar algorithm
• Implementation and results
• Future work

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Future Work

• Bigger multi-chip router layouts
• Faster Rotating Crossbar algorithms
• Efficient route look-up on larger routing tables
• Intermixing switch fabric with computation
• Virtual Private Networks (payload encryption)
• Intrusion Detection Systems (traffic sniffing)
• Per-flow compression (save bandwidth)
• Quality of Service

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And, More Importantly,...

• Build a physical router!

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Conclusions

• Implemented a gigabit IP router on Raw
• Mapped dynamic communication to static network
• Can intermix switch fabric with computation
• High-bandwidth I/O allows performance of custom
  ASIC processors

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Questions?
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(No Transcript)
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Current Design Points

• Edge router or switch fabric of a core router,
  NOT a core router
• WHY?
• External buffering of bandwidth-delay product ?
  no Fair Queueing, etc.
• Route lookup within a single tiles cache (8k
  words, 32bit word) ? too small!

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Static vs. Dynamic

• Static networks stream high-bandwidth IP traffic
• Dynamic network delivers low-bandwidth control
  messages
• Decoupling of data and control communication