A Digital Design Flow for Secure Integrated Circuits

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A Digital Design Flow for Secure Integrated
Circuits

• Written By Kris Tiri and Ingrid Verbauwhede
• Presented By William Whitehouse

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Secure Digital Design Flow

• Purpose
• Wave Dynamic Differential Logic
• Differential Pair Routing
• Proposed Design Flow
• Experimental Results
• Comments

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Purpose

• Small integrated circuits are vulnerable to
  side-channel attacks (SCA). The authors present a
  digital VLSI design flow to create secure
  power-analysis-attack-resistant ICs. The proposed
  design flow uses a technique to balance the power
  consumption of the logic gates. It is independent
  of the cryptographic algorithm or arithmetic
  implemented.

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Wave Dynamic Differential Logic

• Wave Dynamic Differential Logic (WDDL) was chosen
  for its constant power consumption
• WDDL Library contains 37 of 53 basic logic
  functions

WDDL AND-OR-INVERT example
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WDDL Output Voltage

• Demonstration of the output voltage for a WDDL
  gate

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WDDL Load Capacitance

• Load capacitances of differential outputs must be
  matched to achieve constant power consumption
• Load capacitance is made of
• Intrinsic output capacitance
• Interconnect capacitance
• Intrinsic input capacitance
• With the shrinking of the channel length of the
  transistors the interconnect capacitance becomes
  the dominant capacitance

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Interconnect Capacitance

• The WDDL true and false output interconnects are
  routed in parallel such that they are
• on adjacent tracks of the routing grid
• on the same layers
• the same length
• Interconnect must have the same parasitic effects
  (resistance and capacitance)
• Interconnects must be routed to control crosstalk

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Differential Pair Routing

• To add the differential pair routing to the
  secure design flow the authors split the routing
  into two steps
• Fat Wire Routing
• Interconnect Decomposition

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Interconnect Decomposition

• This figure illustrates the interconnect
  decomposition

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Capacitance Comparisons

• Variation of the input capacitance of true/false
  WDDL gates is within 10
• Variation between true/false interconnect
  capacitance of differential pair routing is
  within 20
• Variation between true/false interconnect
  capacitance of regular routing of true/false
  gates is 50

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Proposed Design Flow

• The following is the authors proposed secure
  digital design flow

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Additional Design Flow Stages

• New stages include Cell Substitution and
  Interconnect Decomposition

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Experimental Results

• Subset of DES algorithm

Secure Reference
Size (um2) 12880 3782
Mean Energy Consumption (pJ) 27.1 4.6
Normalized Energy Deviation 6.6 60
Normalized Standard Deviation 0.9 12
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Transient Simulation

• A differential power analysis (DPA) attack was
  performed on the two designs.

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Prototype IC

• Secure and Insecure AES Core were design and
  fabricated on the same die

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Power Analysis of Prototype IC
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DPA Attack on Prototype IC
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Comments

• Good case for use of differential gates
• Designs SCA resistant ICs
• Easy to add into digital design flow and not much
  overhead
• Independent of cryptographic algorithm
• Larger area and power consumption
• Much Lower throughput

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Improvements

• Only use WDDL gates and differential pair routing
  on some blocks of the design
• The WDDL library only has 70 of basic logic
  functions in a standard cell library

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Questions

• If you have any questions please email me at
• wdwhiteh_at_iastate.edu