CSL718 : Main Memory

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CSL718 Main Memory

• 6th Mar, 2006

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Requirements

• CPU Main Memory word transfers
• Cache Main Memory block/line transfers (words
  also in WT)
• I/O Main Memory large block transfers
• Use of write buffers
• Out of order execution
• How to speed-up transfer?

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Use Wider Bus

• Wide bus between cache and main memory Multiple
  words transferred in parallel

Memory
CPU
Cache
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Use Faster Bus

• Improve the throughput, not necessarily the
  latency

latency
first word
subsequent words
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Interleaved Memory
Memory
Memory
CPU
Cache
Memory
Memory
bank 0
bank 1
bank 2
bank 3
0 4 8 12
1 5 9 13
2 6 10 14
3 7 11 15
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Interleaved Memory Performance

• Given
• L line size
• m number of interleaved modules
• Ta memory access time
• Tc memory cycle time
• Tbus bus cycle time
• Find
• Tline line access time

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Case I
Ta
Tbus
Tbus
Tbus
first word
subsequent L -1 words
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Case II
Tc
Ta
m . Tbus
m . Tbus
first m words
next m words
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Case III
Ta
Tc
Tc
Tc
Tbus
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Semiconductor Memory Technology

• Fast memory for cache - Static RAM (SRAM)
• High density main memory - Dynamic RAM (DRAM)
• Non volatile memories for embedded systems - ROM,
  PROM, EPROM, Flash

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DRAM Structure
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Enhancing DRAM Performance

• Multiple arrays of cells
• Access multiple bits in a row (sequentially
  randomly)
• Synchronous interface rather than asynchronous
  interface
• Transfer data on both edges of clock

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DRAM Technologies

• Fast Page Mode (FPM) DRAM
• Extended Data Out (EDO) DRAM
• Burst Extended Data Out (BEDO) DRAM
• Synchronous DRAM (SDRAM)
• Synchronous-Link DRAM (SLDRAM)
• Double Data Rate SDRAM (DDR SDRAM)
• Direct Rambus DRAM (DRDRAM)
• Video RAM (VRAM) dual ported

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Memory Modules in PCs

• SIMM (single in-line memory module) Have 72 or
  30 pins. Support 32-bit and 16-bit data
  transfers.
• DIMM (dual in-line memory module) Have 168 pins.
  Support 64-bit data transfers.

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Fast Page Mode (FPM) DRAM

• Row address selects a page (row)
• Bits in a page selected by column addresses

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Extended Data Out (EDO) DRAM

• extends the time for which output data is valid,
  easing timing issues between the CPU and RAM and
  enhancing performance

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Burst EDO (BEDO) DRAM

• A variant on EDO DRAM
• Read or write cycles are batched in bursts of
  four
• Two LSBs of the column address get modified
  internally to produce each address of the burst
  sequence

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SDRAM

• Synchronizes itself with the CPU's bus
• One block of data can be sent to the CPU while
  another is being prepared for access
• About three times faster than conventional FPM
  RAM and about twice as fast EDO DRAM and BEDO
  DRAM
• Standards PC66, PC100, PC133, PC150 (PC150
  means 150 MHz, peak bandwidth upto 1.2GB/s)
• DDRSDRAM PC1600, PC2100, PC2700, PC3200
  figure refers to MB/s

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SDRAM Organization
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RDRAM

• Highest bandwidth per pin
• A highly efficient packet-based protocol,
  pipelined command and data, low-voltage signaling
  and precise clocking to minimize skew between
  clock and data lines
• densities up to 256Mbit
• speeds from 800MHz to 1200MHz
• single-, dual- or quad-channel RIMM modules to
  support bandwidths from 1.6 GB/sec to 10.7 GB/sec
  and system memory capacities up to 8GB
• Match Pentium 4s system bus 400/533MHz

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RDRAM Organization
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RIMM
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Comparison of some DRAMs
Memory Typical System Ideal Timing
Usual DRAM Technology Bus Speeds
Speed (ns) DRAM 4.77-40
5-5-5-5 or worse 80-150 FPM 16-66
5-3-3-3
60-80 EDO 33-75
5-2-2-2 50-60 BEDO
60-100 5-1-1-1
25 SDRAM 60-150 4-1-1-1
6-12 (PC100)
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Fast Page Mode DRAM
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Interleaving with Fast Page Mode
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References

• http//home.cfl.rr.com/eaa/MemoryTypes.htm
• http//home.cfl.rr.com/bjp/ComputerMemory.htm
• http//www.pctechguide.com/03memory.htm
• Flynns Book
• Hennessy Pattersons Book