Reconfigurable Processing Building Blocks for Spacecraft MAPLD 2004 J. R. Marshall

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Reconfigurable Processing Building Blocks for
SpacecraftMAPLD 2004J. R. Marshall
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Agenda

• Mission Needs for Reconfigurable Processing
  Elements
• Challenges to Realize Capabilities
• Reconfigurable Element Taxonomies
• Potential Reconfigurable Elements and
  Architectures
• Lessons Learned and Summary

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Todays Needs for Processing Building Blocks

• Modular Interchangeable Pieces, Mix and Match
• Configurable Plug and Play at Assembly
• Reconfigurable Change Mission after Launch
• Responsive Very Quick Turnaround
• Power Efficient
• Scalable
• ASICs to FPGAs to GPPs
• Single to Busses to Fabrics

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Missions

• Micro-Satellites
• Software Defined Radios
• Reconfigurable Transceivers
• Energy Measuring Systems
• Communications Systems
• Science Payloads
• Combinations of Objectives and Applications
• Very Long Timeframes
• Quick Response Timeframes

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Value to Missions

• Improve Performance without Hardware Upgrade
• Rapid Response to New Requirements
• Respond to Changing Environments or Multiple
  Missions
• Shorter Development / Testing Cycles
• Smaller Number of Unique Elements
• Higher Reliability and Fault Tolerance
• Significant Commercial Industry Focus
• Leverages Many Complementary Technologies

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Ultimate Goals

• Self Aware or Cognitive
• Integrated Elements across all Materials
• Lowest Power Adaptable and Energy Conserving
• Lasting State Non Volatile and Radiation
  Hardened
• Yet with Universal, Standard Interfaces
• Result a Reconfigurable Putty, that is anything
  but Silly!

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Radiation Challenges

• Total Ionizing Dose
• Technologies Improving as Size Decreases
• Single Event Effects
• Getting Worse Must Continue to be Focus
• Current Mitigation
• Fuse-Based (modular and configurable not
  reconfigurable)
• TMR Circuits
• Readback, Check and Reload of Configuration
  Memory
• Mix and Match of Appropriate Elements vs.
  Application
• Future Mitigation
• NonVolatile Radiation Hardened Configuration
  Memory
• HBD or Radiation Hardened Memory and Logic

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Clocking

• Special Emphasis Needed Here across
  Reconfigurable Elements
• Many standard interfaces have built in Clocks
• PLLs Enable Lower Speed Clocks except when data
  must be tagged to the highest Frequency
• Fastest Needs are for Point-to-Point Connection
• Must be able to share data across multiple
  devices on same clock cycle

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Infrastructure

• Can Not Be Ignored
• Common Infrastructure Block
• Pre Tested I/Os
• Internal Application Design Easier
• Enables Mixing and Matching of Cores
• Cores
• Both Logic and Memory Elements
• Need internal Connection Medium for Devices
• Pre-tested
• Parameterized as Much as Possible increases
  Flexibility
• Support Tools and Environment
• Leverage COTS Tools
• Overlap Mission Users with Developers to Maximize
  Ease of Use and Testing

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Concentration of Interfaces and Power

• Current FPGAs in Very High I/O (1000 Pins)
  Packages
• Maximum Capability Requires
• Maximize Universal Interconnects
• Maximize Thermal Paths
• Maximize Thermal Cycling Capabilities
• Maximize Modular Elements
• Must be Space Qualifiable
• Mechanical Challenges
• High Density Reliable Pluggable Connectors
• 3D Structures (daughter cards, etc.) Per Element
  on Backplane
• Fabric Modularity on Backplanes (no SPOF)
• Higher Density on Circuit Boards and Within
  Packages
• Multiple Power Sources and Voltages
• Thermal and Vibration Solutions
• Reliability Challenges
• Higher Fidelity Models

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Reconfigurable Element Taxonomies
MEMS
ATOMIC
STRUCTURES
MATERIALS
PROGRAMMABLE FIXED STATES
INTERCONNECT
FABRIC
WIRES
CHANGEABLE, KNOWN STATES
ANALOG
POWER
EVOLVABLE, REACTIVE, AUTONOMOUS
DIGITAL
MWAVE
DSP
FPGA
ASIC
FILTERS
GPP
GA
S-A
SELF- AWARE, COGNITIVE
XCVRS
PHYSICAL
BREADTH OF CHANGE
USER INTERFACE
TRAINING
TRAINING
DESIGN ENVIRON- MENT
TEST EQUIPMENT
TC INTERFACE
INFRASTRUCTURE
MISSION TESTING
SUPPORT SOFTWARE
ELEMENT LIBRARY
DEVELOPMENT
MISSION
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Interface Hierarchy
BOX
CHIP
CARD or BOARD
On Board or MCM
Backplane Busses
CHIP
CARD or BOARD
Fabrics
External Interfaces
PERIPHERAL
MCM or Hybrid
CHIP
CHIP
CHIP
BACKPLANE
PERIPHERAL
FABRIC
CARD or BOARD
CHIP
CARD or BOARD
CHIP
CHIP
CHIP
SW
CHIP
CHIP
CARD or BOARD
CARD or BOARD
SW
SW
CHIP
CHIP
CARD or BOARD
CARD or BOARD
PERIPHERAL
PERIPHERAL
CARD or BOARD
B O X
B O X
B O X
FABRIC
CHIP
CHIP
CHIP
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Near Term Recommended Electrical Interfaces

• On Board or MCM (chip to chip)
• LVTTL/LVCMOS
• LVDS
• ISA
• PC/104
• PCI / PCI-X (3.3V Signaling)
• PCI Express
• RocketIO or similar transceiver
• Rapid I/O
• HyperTransport
• Backplane Busses or Interconnects
• All LVTTL/LVCMOS
• LVDS
• RocketIO or similar transceiver
• ISA
• CompactPCI (3.3V Signaling)
• PCI-X (3.3V Signaling)
• PCI Express
• VME

• Fabrics
• SpaceWire using LVDS, RocketIO or similar
• RapidIO
• Serial RapidIO
• Ethernet
• InfiniBand
• Star Fabric
• Advanced Switching
• External Interfaces
• LVDS
• RocketIO or similar transceivers
• 3.3V LVTTL/LVCMOS
• RS-422
• PECL
• I2O
• SpaceWire using LVDS, RocketIO or similar
• Serial RapidIO
• IEEE 1394
• MIL-STD-1553B

Green External PHY Blue Recommended
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Current Reconfigurable Elements
6U

• Features
• 50/100 MHz Operation
• 1-3 x 1M gate RAM-Based FPGAs
• Up to 192 MB FPGA-Shared SDRAM
• 1-4 MB FPGA Configuration Memory
• Auto Configuration Readback
• Common Infrastructure Block provides Pre-tested
  Board I/O
• 33 MHz Microcontroller with 256 KB EEPROM and 64
  KB Scratchpad RAM
• 33 MHz CompactPCI I/F
• 1-3x32 Bit 50 MHz Data Ports
• 50 External FPGA I/Os
• Thermistor on each FPGA
• SEM-E Stretch or cPCI 3U/6U Card
• 2 W (Standby) up to 30 W (Max)
• Application Switch in lt 1 sec
• 3 us frame / 20 ms FPGA reload
• Development/Test Environment

3U
SEM-E Stretch
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Reconfigurable Interfaces Architecture
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Lessons Learned

• Must have more standard interfaces
• Infrastructure will enable true reconfiguration
  dont forget mission user and operator training
• Seldom does one processing technology fit all
  needs i.e., mix from GPPs to FPGAs to ASICs
• Must Always Lower Power, period.
• Power, Thermal and Mechanical are true enablers
  for future progress

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Summary

• Modular, Configurable, Reconfigurable, Responsive
  and Scalable driving need for Reconfigurable
  Processing Elements - spans physical, behavior
  and infrastructure
• Starting to see some products in Space expect
  explosion utilizing new technologies in coming
  years with significant gains in performance and
  behavior
• Must find ways to standardize as in CPUs and
  maximize interconnects yet lower power and be
  adaptive to environment
• Someday will have reconfigurable Putty (that is
  not Silly!)