Design Automation for VLSI, MS-SOCs & Nanotechnologies

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Design Automation for VLSI, MS-SOCs
Nanotechnologies Dr. Malgorzata Chrzanowska-Jeske
http//web.cecs.pdx.edu/jeske/
Mixed-Signal System-on-Chip (supported by NSF)
In Mixed-Signal System-on-Chip (MS-SOC) analog
and digital blocks are integrated on the same
substrate, which introduces many design problems
including a substrate noise coupling problem due
to parasitic interactions between blocks through
the common substrate. We develop noise models for
analog and digital blocks that we use in
early-design floorplanining to optimize overall
substrate coupling noise and to avoid costly
redesigns.
Design for Predictability and Productivity
(DFPP) Our research addresses the critical need
of predictability and productivity improvements
required for Ultra Large System Integration
(ULSI) designs manufactured using sub-90nm
technology nodes. These designs have to meet
power and functional performance requirements in
the existence of significant process parameters
variations due to challenges associated with
sub-wavelength lithography and short channel
effects including leakage. Thus, a major
challenge in designing low-noise, low-power,
high-speed reliable systems is to be able to
predict and control system performance parameters
and their distributions. The 2005 ITRS update
enlists the accuracy of optical proximity
correction (OPC) and OPC verification as
difficult challenges for sub-45nm technology
nodes. OPC algorithms have to be applied after
the layout of computational logic cells is
completed. Since the optical neighborhood of the
transistors used in the ULSI system do not
resemble that of the transistor used in the
process technology development phase, the power
and performance statistical distributions become
hard to predict. The objective of this research
is to bring the restricted layout philosophy to
logic gates and interconnects through controlling
geometric dimensions, geometric shapes, locations
and surroundings of circuit components.
Layout-driven Logic Synthesis and Regular
Layout (supported by NSF) Logic synthesis is a
process of translating high-level
(register-transfer level or even behavioral
level) design descriptions to logic gates in
order for the design to be manufactured as ICs.
As the device size shrinks and the number of
devices increases, the synthesis process needs to
use functional properties of the design, and
flexibilities in a Boolean network in order to
meet the ever demanding requirements of delay,
area and power etc. This research explores
symmetry, autosymmetry and unateness properties
of Boolean functions, their efficient computation
algorithms and how to apply them in logic
synthesis. Flexibilities are considered to make
local structural changes to the netlist, while
maintaining the global functionality of the
circuit.

• Selected Publications
• Tao Wan and M. Chrzanowska-Jeske, A Novel
  Net-Degree Distribution Model and its Application
  to Floorplanning Benchmark Generation, accepted
  to Integration, the VLSI Journal, Sept. 2006.
• G. Blakiewicz and M. Chrzanowska-Jeske, Supply
  Current Spectrum Estimation of Digital Cores at
  Early Design, accepted to IEE Proceedings,
  August 2006.
• J. S. Zhang, A. Mishchenko, R. Brayton and M.
  Chrzanowska-Jeske Symmetry Detection for Large
  Boolean Functions Using Circuit Representation,
  Simulation and Satisfiability, Proceedings of
  the IEEE Design Automation Conference, DAC06.
  July 2006.
• J. S. Zhang, M. Chrzanowska-Jeske, A. Mishchenko
  and J, Burch, Linear Cofactor Relationships in
  Boolean Functions, IEEE Trans. On CAD of
  Integrated Circuits and Systems, June 2006.
• M. Chrzanowska-Jeske, A. Mishchenko, Synthesis
  for Regularity using Decision Diagrams,
  Proceedings of IEEE ISCAS05, May 2005.
• Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan
  Mishchenko, Jerry R. Burch, Fast Computation of
  Generalized Symmetries in Boolean Functions,
  Proceedings of IEEE ASP-DAC, January 2005.
• G. Blakiewicz, M. Jeske, M. Chrzanowska-Jeske,
  J. S. Zhang, Substrate Noise Modeling in Early
  Floorplanning of MS-SOCs , Proceedings of the
  the IEEE ASP-DAC, January 2005.
• Y. Xia, M. Chrzanowska-Jeske, B. Wang M. Jeske,
  Using a Distributed Rectangle Bin-Packing
  Approach for Core-based SoC Test Scheduling with
  Power Constraints, Proceedings of IEEE ICCAD
  2003.
• B. Wang, M. Chrzanowska-Jeske, M. Jeske,
  Methods for Efficient use of Lagrangian
  Relaxation for SOC Soft-Module Floorplanning,
  Proceedings of the SOC Conference, September
  2003.
• F. Rafiq, M. Chrzanowska-Jeske, H. H. Yang, M.
  Jeske, N. Sherwani, Integrated Floorplanning
  with Buffer/Channel Insertion for Bus-Based
  Designs," IEEE Trans on Computer-Aided-Design,
  Vol. 22, nr. 6, pp 730-741, 2003.
• M. Chrzanowska-Jeske, Y. Xu, M. Perkowski,
  Logic Synthesis for a Regular Layout, VLSI
  Design, An International Journal of Custom-Chip
  Design, Simulation, and Testing., vol. 12, No. 3,
  2000.
• W. Wang, M. Chrzanowska-Jeske, Optimizing
  Pseudo-Symmetric Binary Decision Diagrams using
  Multiple Symmetries, Proceedings of the IEEE
  International Workshop on Logic Synthesis,
  IWLS98, pp. 334-340, 1998.

Physical design for 3D VLSI ICs With increasing
clock speed of VLSI chips into multi-GHz range
and decreasing transistor's switching time,
interconnect delay due to wiring parasitics has
become one of the dominant issues determining the
chip's performance. One of a possible solution
to reduce wirelength is to move from 2D (two
dimensional, one device layer current VLSI
chips) to 3D chips in which there can be more
than one device layer. The 3D floorplanner is
being developed. We use the sequence-pair
representation and an evolutionary algorithm to
floorplan blocks on all device layers in 3D chip
to optimize area and wavelength.