Xilinx FPGA Design Flow

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Xilinx FPGA Design Flow
Digital System????

• Ping-Liang Lai (???)
•  

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Outline of FPGA Design Flow

• Project Navigator ????
• ???? I? Schematic ????
• ?????? (Project)
• ????? (Schematic) ????
• ???? (Functional Simulation) ???
• Testbench ???
• ???? ?? Modelsim Simulator
• ????
• Implementation Constraints File ???
• Implementation Design
• ???? (Timing Simulation) ??? ?? Modelsim
  Simulator
• Configuration ???
• ????
• ???? II ? Verilog ????

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Project Navigator ???? (1/2)
Multi-document Interface
Source ??
Process Source ??
Transcript ??
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Project Navigator ???? (2/2)

• Source ??
• Sources Tab
• ?? (Project) ???????????FPGA/CPLD
  ????????????????? Design View????????
• Snapshot Tab
• ????????? Snapshot,?? Snapshot ???????????
  Project?
• Library Tab
• ???????? Project ????? Library?
• Processes Source ??
• ?????????????
• Transcript ??
• Console, Error, Warning, Tcl Console, and Find in
  Files.

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Outline of FPGA Design Flow

• Project Navigator ????
• ???? I? Schematic ????
• ?????? (Project)
• ????? (Schematic) ????
• ???? (Functional Simulation) ???
• Testbench ???
• ???? ?? Modelsim Simulator
• ????
• Implementation Constraints File ???
• Implementation Design
• ???? (Timing Simulation) ??? ?? Modelsim
  Simulator
• Configuration ???
• ????
• ???? II ? Verilog ????

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?????? (1/8)

• Step 1 File ? New Project

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?????? (2/8)

• ??? FPGA ???? Spartan 3 XC3S200-FT256

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?????? (3/8)

• Step 2 ?????? Source ?,?? Schematic ????

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?????? (4/8)

• New Source Summary

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?????? (5/8)

• We only need one Source, so Next.

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?????? (6/8)

• We dont need and have any Existing Sources, so
  Next.

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?????? (7/8)

• New Project Summary

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?????? (8/8)
1. ?? Source ?,? Device ?
2. ???????
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Outline of FPGA Design Flow

• Project Navigator ????
• ???? I? Schematic ????
• ?????? (Project)
• ????? (Schematic) ????
• ???? (Functional Simulation) ???
• Testbench ???
• ???? ?? Modelsim Simulator
• ????
• Implementation Constraints File ???
• Implementation Design
• ???? (Timing Simulation) ??? ?? Modelsim
  Simulator
• Configuration ???
• ????
• ???? II ? Verilog ????

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Schematic ????? (1/5)

• Schematic ?????

Add I/O Maker
Add wire
Add Symbol
Add Net Name
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Schematic ????? (2/5)

• Step 3 Add ? Symbol and Wire.

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Schematic ????? (3/5)

• Step 4 Add ? IO Maker.

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Schematic ????? (4/5)

• Step 5 Add ? Net name.

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Schematic ????? (5/5)

• Step 6 Tool ? Check schematic, and check no
  error and Save.

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Outline of FPGA Design Flow

• Project Navigator ????
• ???? I? Schematic ????
• ?????? (Project)
• ????? (Schematic) ????
• ???? (Functional Simulation) ???
• Testbench ???
• ???? ?? Modelsim Simulator
• ????
• Implementation Constraints File ???
• Implementation Design
• ???? (Timing Simulation) ??? ?? Modelsim
  Simulator
• Configuration ???
• ????
• ???? II ? Verilog ????

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??????? (1/12)

• Step 7 Source for Behavioral Simulation,?? fa
  (fa.sch),add new source,??? fa_tbw?

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??????? (2/12)

• We only have one source, so Next.

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??????? (3/3)

• New Source Summary

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??????? (4/12)
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3
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??????? (5/12)

• Step 8 ?? input ?????,n inputs ? 2n input
  combinations.

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??????? (6/12)

• Step 9 Modelsim Simulator ? Simulate Behavioral
  Model (Double click mouse left key 2 times).

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??????? (7/12)

• ?? Modelsim Simulator?,You can see Error
  Loading .

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??????? (8/12)

• Step 10 Select work ? Compiler AND2, OR3, and
  XOR2. (file path C//Xilinx/9.2i/ISE/verilog/src/
  unisims)

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??????? (9/12)

• Step 11 In fa_tbw, Right click ? Simulate

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??????? (10/12)

• Step 12 Right Click fa_tbw to select Add ? To
  Wave ? All items in region.

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??????? (11/12)

• Behavioral Waveform Window

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??????? (12/12)

• Step 14 Run all, and Step 15 Zoom fit.

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Outline of FPGA Design Flow

• Project Navigator ????
• ???? I? Schematic ????
• ?????? (Project)
• ????? (Schematic) ????
• ???? (Functional Simulation) ???
• Testbench ???
• ???? ?? Modelsim Simulator
• ????
• Implementation Constraints File ???
• Implementation Design
• ???? (Timing Simulation) ??? ?? Modelsim
  Simulator
• Configuration ???
• ????
• ???? II ? Verilog ????

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Implementation Constraints File ??? (1/8)

• Step16 Sources for Synthesis/Implementation
• Step 17 ?? fa.sch,Project ? New Source

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Implementation Constraints File ??? (2/8)
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Implementation Constraints File ??? (3/8)

• Step 18 ?? fa.ucf,User Constraints ? Assign
  Package Pins.

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Implementation Constraints File ??? (4/8)

• Xilinx PACE ??

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Implementation Constraints File ??? (5/8)

• Step 19 ??Package View,??Design Browser ? I/O
  Pins

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Implementation Constraints File ??? (6/8)

• Step 20 ?? Spartan-3 FPGA XC3S200-FT256 ?
  Datasheet
• Slide Switches
• LEDs

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Implementation Constraints File ??? (7/8)

• ???,File ? Save?

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Implementation Constraints File ??? (8/8)

• ?? Edit Constraints (Text)

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Outline of FPGA Design Flow

• Project Navigator ????
• ???? I? Schematic ????
• ?????? (Project)
• ????? (Schematic) ????
• ???? (Functional Simulation) ???
• Testbench ???
• ???? ?? Modelsim Simulator
• ????
• Implementation Constraints File ???
• Implementation Design
• ???? (Timing Simulation) ??? ?? Modelsim
  Simulator
• Configuration ???
• ????
• ???? II ? Verilog ????

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Implement Design (1/6)

• Step 21 Implement Design

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Implement Design (2/6)
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Implement Design (3/6)

• ???Place Route ? View/Edit Routed Design (FPGA
  Editor),?????? LUT ??????

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Implement Design (4/6)

• FPGA ???????? (Design Summary ? Summary)

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Implement Design (5/6)

• Pinoout Report (Design Summary ? Pinout Report)

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Implement Design (6/6)

• ??????? Generate Post-Place Route Static
  Timing ? Analyze Post-Place Route Static Timing.

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Outline of FPGA Design Flow

• Project Navigator ????
• ???? I? Schematic ????
• ?????? (Project)
• ????? (Schematic) ????
• ???? (Functional Simulation) ???
• Testbench ???
• ???? ?? Modelsim Simulator
• ????
• Implementation Constraints File ???
• Implementation Design
• ???? (Timing Simulation) ??? ?? Modelsim
  Simulator
• Configuration ???
• ????
• ???? II ? Verilog ????

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???? (Timing Simulation)

• ? Functional Simulation ??????

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2
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Outline of FPGA Design Flow

• Project Navigator ????
• ???? I? Schematic ????
• ?????? (Project)
• ????? (Schematic) ????
• ???? (Functional Simulation) ???
• Testbench ???
• ???? ?? Modelsim Simulator
• ????
• Implementation Constraints File ???
• Implementation Design
• ???? (Timing Simulation) ??? ?? Modelsim
  Simulator
• Configuration ???
• ????
• ???? II ? Verilog ????

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Configuration ??? (1/2)

• Step 22 Generate Programming File

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Configuration ??? (2/2)

• ?? Configure Device (iMPACT)
• Step 22 iMPACT ??,?? Configure devices using
  Boundary-Scan (JTAG) ? Automatically

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Outline of FPGA Design Flow

• Project Navigator ????
• ???? I? Schematic ????
• ?????? (Project)
• ????? (Schematic) ????
• ???? (Functional Simulation) ???
• Testbench ???
• ???? ?? Modelsim Simulator
• ????
• Implementation Constraints File ???
• Implementation Design
• ???? (Timing Simulation) ??? ?? Modelsim
  Simulator
• Configuration ???
• ????
• ???? II ? Verilog ????

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???? II ? Verilog ????

• From Step 2 to choose a Verilog Module, and
  repeat Step3 Step 22.
• Design example 4-bit Ripple Carry Counter

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4-bit Ripple Carry Counter
q0
q1
q2
q3
Ripple Carry Counter
q
q
q
q
clock
T_FF
T_FF
T_FF
T_FF
reset
q
T_FF
d
q
clock
D_FF
reset
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Design Block
Ripple Carry Counter Top Block (ripple_carry_count
er.v)
module ripple_carry_counter (q, clk, reset)
output 30 q input clk, reset T_FF
tff0 (q0, clk, reset) T_FF tff1 (q1, q0,
reset) T_FF tff3 (q2, q1, reset) T_FF
tff4 (q3, q2, reset) endmodule
Flip-flop D_FF (dff.v)
module D_FF (q, d, clk, reset) output q
input d input clk input reset reg
q always _at_ (posedge reset or negedge clk)
if (reset) q 1'b0 else q d endmodule
Flip-flop T_FF (tff.v)
module T_FF (q, clk, reset) output q
input clk, reset wire d D_FF dff0 (q, d,
clk, reset) not n1 (d, q) endmodule
Example
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Stimulus Block
module rcc_testbench reg clk reg reset wire
30 q ripple_carry_counter r1 (q, clk,
reset) initial clk 1'b0 always 5 clk
clk initial begin reset 1'b1 15 reset
1'b0 180 reset 1'b1 10 reset 1'b0 20
finish end initial monitor(time, "Output q
d", q) endmodule
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Design Block and Stimulus Block

• Two styles of stimulus application
• Stimulus block instantiates design block
• Dummy top-level module

Top-Level Block
(Stimulus block)
clk
reset
clk
d_clk
d_reset
reset
Design Block
q
c_q
q
Design Block
Stimulus Block
Fig. 1. Stimulus block instantiates design block
Fig. 2. Stimulus and design blocks instantiated
in a Dummy top-level module