Fast Realization of Video Coders Based on Characteristics of DCT Coefficients

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(?) Fast Realization of Video Coders Based on
Characteristics of DCT Coefficients ?????
??????? Distinguished Lecturer, IEEE Circuits and
Systems Society distinguished lecture
program 95?3?28?(???) 1000 am 1200noon
????????????????? (?) Low-Voltage Nano-Scale
Embedded RAM Dr. Kiyoo Itoh, Fellow IEEE,
Hitachi, Ltd., Central Research
LaboratoryDistinguished Lecturer, IEEE
Solid-State Circuits Society distinguished
lecture program 95?4?17?(???) 1600 1730pm
?? ??????2?105???? 95?4?18?(???) 1000am
1200noon ?? ????????????? (?) Circuit Design
and Innovations in Scaled/Emerging
Technologies Dr. Ching-Te Kent Chuang and Dr.
Shih-Hsien Lo IBM T. J.  Watson Research
Center95?4?25?(???) 1000am
1200noon????????????????? ???? ????????
????????????? IEEE CAS TAIPEI
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http//caiser.nctu.edu.tw/ ????? ?? ??? ???
03-5712121?52983, ??? 03-5712121?59303,

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Fast Realization of Video Coders Based on
Characteristics of DCT Coeficients?????
???????Distinguished Lecturer, IEEE Circuits and
Systems Society distinguished lecture program

• Biography of Dr. J.-F. Kevin Yang
• Dr. J.-F. Kevin Yang received his Ph.D. degree
  from the University of Minnesota, Minneapolis, in
  1988. He is now with the National Cheng Kung
  University as a distinguished professor of the
  Department of Electrical Engineering. He was the
  Chairman of the Center for Computer and
  Communication Research, the National Cheng Kung
  University from 1997 to 2000. Currently, he is
  the Director of Graduate Institute of Computer
  and Communication Engineering, the Director of
  the Electrical and Information Technology Center,
  in the National Cheng Kung University. From 2004,
  he is Chair of IEEE Signal Processing Society,
  Tainan Chapter and the Treasure of IEEE Tainan
  Section. From 2006, he joins Chair Committee as
  the representative of the IEEE Signal Processing
  Region 10. During 2004 - 2005, he is one of
  speakers in the Distinguished Lecturer Program
  selected by the IEEE Circuits and Systems
  Society. He is an Associate Editor and a Guest
  Editor of Special Issue on Advanced Video
  Technologies and Applications for H.264/AVC and
  Beyond of EURASIP Journal of Applied Signal
  Processing. He is an Associate Editor of the IEEE
  Circuits and Devices Magazine. He was the
  Technical Program Co-chairs of the IEEE Asia
  Pacific Conference on Circuits and Systems, 2004
  and the 9th IEEE International Workshop on
  Cellular Neural Networks and Their Applications,
  2005. Currently, he is the Deputy Chairman of
  Taiwanese Video and Audio Compression Consortium.
  From 2006, he is Secretary (Chair-elected), IEEE
  Multimedia Systems and Applications Technical
  Committee. He has published over 70 journal and
  100 conference papers.

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Fast Realization of Video Coders Based on
Characteristics of DCT Coeficients
Jar-Ferr Yang Institute of Computer and
Communication Engineering, Department of
Electrical Engineering, National Cheng Kung
University, Tainan, Taiwan  In image and video
coders, the discrete cosine transform (DCT) is a
basic kernel function for compression of spatial
data redundancy. In this talk, the
characterizations of DCT coefficients are
effectively used to reduce the computation of
DCT-based video decoders and encoder. In video
decoders, the fast implementation of the IDCT
processing will be discussed by using the
coefficient-by-coefficient schemes. The concept
could be extended to the all fast IDCT processors
to reduce the complexity or the computation
power. Besides, the quantized DCT coefficients
provide valuable information for video
postprocessing, which can efficiently remove the
blocky effect resulting from heavy data
quantization. The design of the DCT-based
adaptive postprocessors will be addressed in
details. As to video encoders, we also can
predict zero coefficients directly linked to the
sum of absolute difference (SAD), which is
obtained during motion estimation. If the
all-zero DCT block is predicted, the computations
for successive motion estimation, DCT,
quantization, inverse quantization, and IDCT in
the encoding loop could be totally reduced.
Finally, the preliminary results related to fast
implementation of the advanced video coding
standard, H.264/AVC are also addressed.    
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Low-Voltage Nano-Scale Embedded RAMDr. Kiyoo
Itoh, Fellow IEEEDistinguished Lecturer, IEEE
Solid-state Circuits Society distinguished
lecture programHitachi, Ltd., Central Research
Laboratory

• KIYOO ITOH received the B.S. and Ph.D. Degrees in
  Electrical Engineering from Tohoku University,
  Japan, in 1963 and 1976. He is currently a
  Hitachi Fellow. He was a Visiting MacKay Lecturer
  at U.C. Berkeley in 1994, a Visiting Professor at
  the University of Waterloo in 1995, and a
  Consulting Professor at Stanford University in
  2000-2001. He was a Member of the IEEE Fellow
  Committee from1999 to 2002, and an elected AdCom
  Member of IEEE Solid-State Circuits Society from
  2001 to 2003. He is a Distinguished Lecturer of
  the IEEE Solid-state Circuits Society.
•  
• Since 1972 he has led RAM circuit technology at
  Hitachi Ltd He was the lead designer of the
  first prototype for eight generations of Hitachi
  DRAMs ranging from 4Kb to 64Mb. As early as 1988,
  as a pioneer, he initiated circuit inventions and
  developments to reduce subthreshold current of
  MOSFETs even for the active mode, which is
  highlighted today in low-voltage CMOS LSI design.
• He holds over 370 patents in Japan and US. He
  authored three books and three book chapters on
  memory designs, and contributed over 130
  technical papers and presentations, many of them
  invited, in IEEE journals and conference
  proceedings.
•  
• Dr. Itoh has won 18 honors in US, Europe, and
  Japan. They include the IEEE Paul Rappaport Award
  in1984, the Best Paper Award of ESSCIRC90, the
  1993 IEEE Solid-State Circuits Award, and the
  2006 IEEE Jun-ichi Nishizawa Medal. He is an IEEE
  Fellow. In Japan, his awards include the National
  Invention Award in 1989, the Commendation by the
  Minister of State for Science and Technology in
  1997, and the National Medal of Honor with Purple
  Ribbon in 2000.
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IEEE DLP in Taiwan Title of my Talk Low-Voltage
Nano-Scale Embedded RAMs  
Abstract  RAM cells and peripheral logic circuits
of low-voltage nano-scale embedded RAMs are
described. In particular, essential differences
between the one-transistor one-capacitor (1-T)
DRAM cell and the six-transistor (6-T) SRAM cell
are clarified in terms of low-voltage operations.
In addition, state-of-the-art circuits and
devices to reduce subthreshold currents and
variations in speed and leakage caused by PVT
(process, voltage, and temperature) variations
are described in detail.   In this talk, first,
general trends in low-voltage RAMs are explained.
Second, challenges to low-voltage RAM cells and
peripheral logic circuits are clarified. Third,
RAM cell issues are discussed. Here, the
low-voltage limitation of the 1-T cell and the
6-T cell is investigated in terms of signal
charge, signal voltage, noise, and cell size.
Suppression of the ever-increasing
threshold-voltage (VT) variation with device
scaling, which seriously degrades the sense
margin of the 1-T cell and the voltage margin of
the 6-T cell, the ECC circuit to cope with the
ever-increasing soft-error rate and VT variation,
and power-supply controls of the 6-T cell are
also explained. Fourth, peripheral circuits are
discussed with respect to leakage reduction and
compensation for speed variations caused by VT
variations. Fully-depleted-SOI devices and
circuits to reduce the variations are also
explained. Finally, two approaches are
envisioned, which are high-VDD bulk-CMOS for
low-cost RAMs and low-VDD FD-SOI for high-speed
low-power RAMs.  
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Circuit Design and Innovations in
Scaled/Emerging Technologies
Ching-Te Chuang and Shih-Hsien Lo   IBM T.
J. Watson Research Center, Yorktown Heights, NY
10598, U. S. A.  Phone [phone], Fax
1-914-945-1358, e-mail ctchuang_at_us.ibm.com,
shlo_at_us.ibm.com  BIOGRAPHY Ching-Te Chuang   
Ching-Te Chuang received the B.S.E.E. from
National Taiwan University, Taipei, Taiwan in
1975 and Ph.D. in Electrical Engineering from
University of California, Berkeley, CA in 1982. 
He joined IBM T. J. Watson Research Center,
Yorktown Heights, NY in 1982, working on scaled
bipolar devices, technology, and circuits. From
1986 to 1988, he was Manager of the Bipolar VLSI
Design Group, working on low-power bipolar
circuits, high-speed high-density bipolar SRAMs,
multi-Gb/s fiber-optic data-link circuits, and
scaling issues for bipolar/BiCMOS devices and
circuits. Since 1988, he has managed the High
Performance Circuit Group, investigating
high-performance logic and memory circuits.
Since 1993, his group has been primarily
responsible for the circuit design of IBMs
high-performance CMOS microprocessors. He has
also been personally responsible for evaluating
scaled/emerging technologies, such as PD/SOI,
UT/SOI, strained-Si devices, hybrid orientation
technology, and multi-gate/FinFET devices, for
high-performance logic and memory applications.
He has received 2 Outstanding Technical
Achievement Awards, 5 Research Division Awards,
and 9 Invention Achievement Awards from IBM.  
Dr. Chuang served on the Device Technology
Program Committee for IEDM in 1986 and 1987, and
the Program Committee for Symposium on VLSI
Circuits from 1992 to 2006. He was elected an
IEEE Fellow in 1994 For contributions to
high-performance bipolar devices, circuits, and
technology". He has authored many invited papers
in international journals and presented numerous
plenary, invited or tutorial papers/talks at
international conferences such as International
SOI Conf., DAC, VLSI-TSA, ISSCC Microprocessor
Design Workshop, VLSI Circuit Symposium Short
Course, ISQED, ICCAD, APMC, and VLSI-DAT, etc. He
was the co-recipient of the Best Paper Award at
the 2000 IEEE International SOI Conference. He
holds 17 U.S. patents with another 15 pending.
He has authored or coauthored over 215 papers.
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Circuit Design and Innovations in Scaled/Emerging
Technologies
Shih-Hsien LoIBM T. J. Watson Research Center,
P.O. Box 218, Yorktown Heights, NY 10598Office
[phone] / Tie-line 862-2211 / Fax (914)
945-1358E-mail shlo_at_us.ibm.com
Dr. Lo received the B.S. degree in electrical
engineering from National Cheng-Kung University
in 1986 and the M.S. and Ph.D. degrees in
electronics from National Chiao-Tung University
in 1988 and 1991, respectively. From July 1991 to
May 1993, he served in the military as a Second
Lieutenant. From 1993 to 1995, he was with
National Nano Device Laboratories, Taiwan, where
he was a Research Scientist working on 0.25-mm
CMOS device design and process integration. In
1995 Dr. Lo was recruited by the Exploratory
Devices and Circuits group of the Silicon
Technology Department at the IBM Thomas J. Watson
Research Center, Yorktown Heights, New York. His
researches focused on the areas of ultra-thin
oxide reliability characterization and modeling,
and electrical characterization of Si-based small
geometry devices. From 1997 to 2000, Dr. Lo was
with the IBM Semiconductor Research and
Development Center, East Fishkill, New York. He
first joined the CMOS 7S team working on 0.22-mm
bulk CMOS technology development, which first
offered the Cu BEOL in the industry. Then he led
0.18-mm SOI CMOS device design and
characterization. Since 2000, Dr. Lo has been
with VLSI Design Department at T.J. Watson
Research Center, involving in several
high-performance PowerPC microprocessor designs,
including Power4, Power5, CELL and
next-generation low-power blade server. He is
also leading CMOS technology benchmarking and
works based on circuit simulation and hardware
design. He has received the IBM Microelectronics
General Managers Excellence Award three times,
in 1997, 1998, and 1999.
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Ching-Te Chuang and Shih-Hsien Lo IBM T. J.
Watson Research Center, Yorktown Heights, NY
10598, U. S. A.  Phone [phone], Fax
1-914-945-1358, e-mail ctchuang_at_us.ibm.com,
shlo_at_us.ibm.com  
Circuit Design and Innovations in Scaled/Emerging
Technologies
  Abstract   This talk reviews the
challenges of high-performance digital design in
nanoscale CMOS technology and opportunities
offered by emerging technologies such as
strained-Si devices, hybrid orientation
technology, and multi-gate/FinFET devices.
Circuit design considerations in these emerging
technologies are addressed. Examples of novel
power-gating structures in hybrid orientation
technology are then given. Novel logic circuit
topologies and SRAM cell structures exploiting
the back-gate control or independent-gate control
in multi-gate/FinFET device structures are
discussed.