CMOS Digital System Design

1
CMOS Digital System Design

• MOS Transistor DC Operation

2
Threshold Voltage Vt

• Vgs lt Vt nMOS channel is cut off
• Vt lt Vgs nMOS channel conducts
• Vgs lt Vt pMOS channel conducts
• Vt lt Vgs pMOS channel is cut off

3
Enhancement Mode Transistors Depletion Mode
Transistors

• Enhancement modechannel is cut off when Vgs 0
• Depletion modechannel conducts when Vgs 0
• Most CMOS ICs use enhancement-mode transistors.

4
n-MOS Channel Layers, Page 1

• When Vgs 0,drain-to-substrate is
  reverse-biased pn junction.
• When Vgs gt 0,positive electric field in channel
  under gate
• repels holes
• attracts electrons

5
n-MOS Channel Layers, Page 2

• When Vgs ltlt Vt
• Mobile positive holes in p-type channel in
  substrate are evenly distributed.
• Called accummulation layer
• When Vt lt Vgs
• Holes are repelled, causing a depletion region
  under the gate.
• Called depletion layer

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n-MOS Channel Layers, Page 3

• When Vt ltlt Vgs
• Electrons are attracted, causing a conductive
  layer under the gate.
• Called inversion layer

7
n-MOS Operating Regions, Page 1

• When Vds 0
• Depletion and inversion layers uniform depth
  along length of channel
• When Vds gt 0
• Depletion and inversion layers same depth at
  source end of channel as for Vds 0
• Inversion layer tapers off linearly toward drain
  end

8
n-MOS Operating Regions, Page 2

• When Vds lt Vgs Vt
• Inversion layer becomes deeper as Vgs increases
• Ids depends on both Vgs and Vds.
• Called linear region.
• Also called resistive region.
• Also called nonsaturated region.
• Also called unsaturated region.

9
n-MOS Operating Regions, Page 3

• When Vds gt Vgs Vt
• Vgd lt Vt.
• Inversion layer pinched-off no longer reaches
  drain from source end of channel
• Electrons instead injected into depletion layer,
  then accelerated toward drain
• Ids depends only on Vgs, independent of Vds.
• Called saturated region

10
Body Effect

• When have series-connected nMOS devices, only the
  bottom one has source connected to GND.
• Others have Vsb (Vsource Vsubstrate) gt 0
• For those, have greater gate-channel voltage
  difference
• Increase in Vt.

11
Cutoff Region DC Equation

• For Vgs lt Vt
• Ids 0

12
Nonsaturation Region DC Equation

• For 0 lt Vds lt Vgs Vt
• Ids Beta((Vgs Vt)Vds - Vds2 / 2)
• Beta MOS transistor gain factor

13
Saturation Region DC Equation

• For 0 lt Vgs - Vt lt Vds
• Ids Beta(Vgs Vt)2 / 2
• Beta MOS transistor gain factor (
  (mu)(epsilon) / tox )( W / L )
• mu channel carrier mobility
• epsilon gate insulator permittivity (SiO2)
• tox gate insulator thickness
• W / L channel dimensions

14
LOW Noise Margin

• VIL LOW input voltage
• NML LOW noise margin
• Unity gain point, slope -1
• VIL 2.3 volts
• NML 2.3 volts

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HIGH Noise Margin

• VIH HIGH input voltage
• NMH HIGH noise margin
• Unity gain point, slope -1
• VIH 3.3 volts
• NMH 1.7 volts

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Differential Amplifier, Page 1

• Pair of nMOS transistors,each with a pull-up
  resistor
• Sources connectedthrough constant-current source
  to ground

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Differential Amplifier, Page 2

• If Vin1 and Vin2 change equally from
  Vquiescent,Vout1 and Vout2 stay the same.
• If only Vin1 changes
• current changes one way in resistor 1 and the
  other way in resistor 2
• So Vout1 changes one way and Vout2 changes the
  other.

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Differential Amplifier, Page 3

• Common Mode Gain low
• Differential Gain high
• CMRR Common Mode Rejection Ratio
  Differential Gain/Common Mode Gain
• Good for rejecting common mode noiseon input
  pins
• Used in RAM sense amplifiers

19
Current Mirror

• Pair of nMOS transistors with gates tied together
• Tie drain of side device to its gateto put it in
  saturation
• Feed constant current in side transistor
• Identical current will flow in other transistor,
  since they are in saturation and Vgs1 Vgs2.

20
Tri-State Driver

• Inverter followed by a pass gate
• For same size n- and p-devices, half the speed of
  inverter alone
• Can omit connection between inverter devices
• Used in bus drivers and latches
• Can be drawn as one gate
• (Tri-State is a registered trademark of
  National Semiconductor Corporation.)

21
Junctions and Diodes

• At pn junction, junction diode formed
• At metal-semiconductor junction,creates either
• Ohmic contact, or
• Schottky diode (used extensively for
  high-frequency, low-noise mixer and switching
  circuits).
• Only ohmic in most CMOS processes

22
Diode DC Equation

• I current in a diode Ad Is(exp(qV/kmt)
  1), where
• Ad area of the diode
• Is the saturation current/unit area
• q the charge of an electron
• k Boltzmann's constant
• t temperature
• m approx. 2.0 for pn-junction diodes, and
  approx. 1.2 for Schottky diodes

23
BiCMOS Drivers

• With extra processing steps added to a CMOS
  process, can build useful NPN transistors
• NPN has high current gain
• Can improve output drive of CMOS inverter