UF Vision and Capabilities

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UF Vision and Capabilities

• Alan D. George, Ph.D
• CHREC Director and
• UF Site Director

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University of Florida

• Flagship and land-grant university in State of
  Florida
• 4th largest university in US is in 4th most
  populous state
• Florida is among 5 largest universities in US
• 50,000 students, 2000-acre campus, gt500M/yr in
  RD (2005)
• Member, Association of American Universities
  (AAU)
• AAU prestigious list of leading research
  universities in US and Canada
• Florida is one of only 17 public, land-grant
  universities in AAU
• Florida is one of only 6 Southeastern schools in
  AAU
• Duke, Emory, Florida, North Carolina, Vanderbilt,
  Virginia
• Student enrollment among finest in nation (2005)
• 2 in National Merit Scholars (second only to
  Harvard)
• 4 in National Achievement Scholars (after
  Harvard, Yale, Stanford)
• 1 in both categories among public universities
• Engineering graduate school at Florida ranked in
  top 25 (US News 05)
• Did you know? First digital computer invented by
  UF graduate in EE
• John Vincent Atanasoff, UF BSEE 1925, ISU
  Atanasoff-Berry Computer

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What is a Reconfigurable Computer?

• System capable of changing hardware structure to
  address application demands
• Static or dynamic reconfiguration
• Reconfigurable computing, configurable computing,
  custom computing, adaptive computing, etc.
• Typically a mix of conventional and
  reconfigurable processing technologies
  (control-flow, data-flow)
• Enabling technology?
• Field-programmable hardware (e.g. FPGAs)
• Applications?
• Broad range satellites to supercomputers!
• Faster, smaller, cheaper, less power heat, more
  versatile

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When and where do we need RC?

• When do we need RC?
• When performance versatility are critical
• Hardware gates targeted to application-specific
  requirements
• System mission or applications change over time
• When the environment is extremely restrictive
• Limited power, weight, area, volume, etc.
• Limited communications bandwidth for work offload
• When autonomy and adaptivity are paramount
• Where do we need RC?
• In conventional HPC systems clusters where apps
  amenable
• Field-programmable hardware fits many demands
  (but certainly not all)
• High DOP, finer grain, direct dataflow mapping,
  bit manipulation, selectable precision, direct
  control over H/W (e.g. perf. vs. power)
• In space, air, sea, undersea, and ground systems
• Embedded deployable systems can reap many
  advantages w/ RC

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Research Challenge Stack
Performance Prediction Performance Analysis Nume
rical Analysis Languages Compilers System Serv
ices Portable Libraries System Architectures De
vice Architectures

• Performance prediction
• When and where to exploit RC?
• Performance analysis
• How to optimize complex systems and apps?
• Numerical analysis
• Must we throw DP floats at every problem?
• Programming languages compilers
• How to express achieve multilevel parallelism?
• System services
• How to support variety of run-time needs?
• Portable core libraries
• Where cometh building blocks?
• System architectures
• How to scalably feed hungry FPGAs?
• Device architectures
• How will/must FPLD roadmaps track for HPC or HPEC?

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Bridging the Gaps

• Vertical Gap
• Semantic gap between design levels
• Application design by scientists programmers
• Hardware design by electrical computer
  engineers
• We must bridge this gap to achieve full potential
• Better programming languages to express
  parallelism of multiple types and at multiple
  levels
• Better design tools, compilers, libraries,
  run-time systems
• Evolutionary and revolutionary steps
• Emphasis integrated SW/HW design for multilevel
  parallelism
• Horizontal Gap
• Architectures crossing the processing paradigms
• Cohesive, optimal collage of CPUs, FPGAs,
  interconnects, memory hierarchies,
  communications, storage, et al.
• Must we assume simple retrofit to conventional
  architecture?

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Example DM system for NASA
Dependable Multiprocessor (DM)

• 1st Space Supercomputer
• In-situ sensor processing
• Autonomous control
• Speedups of 100? and more
• Will be first fault-tolerant, reconfigurable,
  parallel computer in space (Feb. 09)
• Infrastructure for fault-tolerant HPEC in space
• Robust system services
• Fault-tolerant MPI services
• FPGA services
• Application services
• Standard design framework
• Providing earth space scientists a transparent
  interface to DMs various resources

First Mission ST-8 Feb'09 launch
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Related Lab Facilities at Florida

• Powerful new RC cluster (name Delta)
• New cluster of 16 Xeon servers (3.2GHz, 32GB
  memory)
• Each server equipped with Nallatech H101 App
  Accelerator
• Xilinx V4 LX100 user FPGA (supported by several
  other FPGAs)
• One bank of 512MB DDR2 SDRAM (4GB/s bandwidth)
• Four banks of 4MB DDR2 SSRAM (2GB/s bandwidth
  each)
• Four MGT Serial I/O channels (2.5Gb/s each)
• 10Gb/s low-latency communication path directly
  between FPGAs!
• All servers interconnected by 20Gbps/link DDR
  InfiniBand
• Made possible by donations discounts from key
  vendors shown
• Cray XD1 reconfigurable supercomputer
• Single-chassis, six-node multiprocessor/FPGA
  server
• 12 Opteron 250 processors (2.4 GHz), two per node
• 24GB of main memory, 4GB per node
• 6 Xilinx Virtex-2 Pro 50 user FPGAs (speed grade
  -7), one per node
• High-speed RapidArray interconnect between nodes
  (8GB/s, 1.3us)
• On loan from Cray to support CHREC research

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Related Lab Facilities at Florida (cont.)

• Altera / Xtreme Data XD1000 reconfigurable server
• Opteron/FPGA SMP server development platform
• Stratrix-II 2S180 user FPGA (largest Altera
  device)
• Direct link between FPGA, CPU, RAM via
  HyperTransport
• Donated by XDI Altera to support CHREC research
• SpaceCube FPGA processing subsystem
• Due from NASA-GSFC in January 07 to support
  CHREC research
• Dual V4 LX60 user FPGAs, Gigabit Ethernet, 32
  LVDS pairs
• Dependable Multiprocessor TRL6 testbed
• On loan from DM prime contractor, Honeywell Inc.
• Prototype for DM system scheduled for orbit on
  ST-8 rocket
• cPCI chassis, 6 PPC boards, 4 ADM-XRC4 boards (V4
  FX55), GigE
• IBM BladeCenter (proposed)
• 16-blade chassis proposed in Nov06 CRI proposal
  from UF to NSF
• Baseline of multicore Xeon blades hope to
  upgrade with V4/V5 blades

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Related Lab Facilities at Florida (cont.)

• PCI/PCI-X and standalone RC development boards
• Variety of commercial and UF-designed RC boards
• Assorted COTS Nallatech, AlphaData, Avnet,
  Xilinx, Celoxica, Tarari
• MathStar FPOA development board (due in January
  07)
• UF RapidIO/FPGA testbed
• UF Network-Attached Reconfigurable Computer
  (NARC)
• UF ARCANE reconfigurable grid (refurbished
  cards, 200 V2Pros)
• Other powerful facilities
• Leverage other HCS Lab resources
• Suite of 12 compute clusters with gt500 processors
• High-speed network testbeds (Quadrics, IB,
  10GigE, etc.)
• Marvel 16-core Linux Opteron SMP, 32GB memory,
  1TB RAID, x16 PCI-e

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Facilities New CHREC Room (LAR317)
Coming in late Dec. 2006
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CHREC Faculty _at_ UF

• Dr. Alan D. George
• Professor of ECE
• Expertise in RC, HPC, and HPEC, for a variety of
  missions apps
• Dr. K. Clint Slatton
• Assistant Professor of ECE and CCE
• Expertise in remote sensing, adaptive signal
  image processing
• Dr. Herman Lam
• Associate Professor of ECE
• Expertise in digital design and distributed
  system services
• Dr. Dapeng "Oliver" Wu
• Assistant Professor of ECE
• Expertise in signal image processing,
  multimedia, info theory
• Other faculty at Florida
• Florida is 4th largest university in US, with
  large and respected schools of engineering,
  health sciences, physical sciences, etc.
• We can draw upon many other faculty experts in a
  broad range of areas

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Y1 Projects Motivations

• Focus on 5 research challenges spanning spectrum
  of RC
• F1 Simulative Performance Prediction with FASE
• Before you invest major in new systems,
  software design, hardware design, better to
  first predict potential benefits
• F2 Performance Analysis Profiling with PPW
• Without new concepts and powerful tools to locate
  and resolve performance bottlenecks, max. speedup
  is extremely elusive
• F3 Application Case Studies HLLs
• RC for HPC or HPEC is relatively new immature
  need to build/share new knowledge with apps
  tools from case studies
• F4 Partial RTR Architecture for Qualified HPEC
  Systems
• Many potential advantages to be gained in
  performance, adaptability, power, safety, fault
  tolerance, security, etc.
• F5 FPLD Device Architectures Tradeoffs
• Leveraging COTS in IT is wonderful, but
  increasing number of options and opportunities
  need to be explored compared

Performance Prediction Performance
Analysis Application Case Studies
HLLs Systems Architecture Device Architecture
F1 F2 F3 F4 F5
Performance, Adaptability, Fault Tolerance,
Scalability, Power, Density
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UF-GWU Collaboration Projections