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SYNTHESIS OF COPPER NANOWIRES WITH NANO-TWIN SUBSTRUCTURES

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SYNTHESIS OF COPPER NANOWIRES WITH NANO-TWIN SUBSTRUCTURES 1Joon-Bok Lee 2Dr. Bongyoung I. Yoo 2Dr. Nosang V. Myung 1Department of Chemical Engineering, A-217 ... – PowerPoint PPT presentation

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Title: SYNTHESIS OF COPPER NANOWIRES WITH NANO-TWIN SUBSTRUCTURES


1
SYNTHESIS OF COPPER NANOWIRES WITH NANO-TWIN
SUBSTRUCTURES
  • 1Joon-Bok Lee
  • 2Dr. Bongyoung I. Yoo
  • 2Dr. Nosang V. Myung
  • 1Department of Chemical Engineering, A-217
    Engineering Quadrangle, Princeton University,
    Princeton, NJ 08544-5263, USA
  • 2Department of Chemical Engineering, University
    of California, Riverside, CA 92521, USA

2
Outline
  • Purpose of Research
  • Usage of copper nanowires in VLSI (very-large
    scale integration)
  • Objective of Research
  • Experimental Procedures
  • Copper thin film electrodeposition
  • Template-based copper nanowire fabrication
  • Results and Discussions

3
Introduction
  • Integrated circuit
  • Discovery in 1970-driving force in advent of
    computer systems
  • Contain transistors and other semiconducting
    devices
  • metal interconnections that serve as
    interconnections for each component
  • 1997 Electrodeposited Copper replaces sputtered
    Aluminum as interconnecting material
  • Much higher conductivity and lower
    electromigration

4
Introduction
  • Advancements in technology? increasing
    interconnections in smaller areas
  • International Technology Roadmap for
    Semiconductors (ITRS) 2005 100 million
    transistors, 100,000 I/O in 30nm2 chips by 2015
  • Copper wires must also be reduced to the
    nanometer scale
  • Need high electrical conductivity and tensile
    strength

5
A cross section of a microchip showing copper
interconnections.
6
Introduction
  • strength of materials increase with decreasing
    grain sizes that form the materials
  • Smaller grain sizes give greater grain boundaries
    (GB)
  • GBs resist propagation of dislocations
  • But GBs also scatter electrons-higher resistance
  • Twin Boundary (TB) blocks dislocation but
    maintains conductivity
  • Optimum find methods to make nanowires with TBs
  • No known attempts in literature or otherwise

7
  • An example of twin
  • boundaries found
  • within specially
  • prepared copper
  • thin film samples

Grain Boundary
8
Objective
  • Understand effect of electrodeposition conditions
    for synthesizing copper nano-twinned nanowires
  • Investigate meterials properties, including
    morphology and microstructures, of copper
    nanowires
  • Investigate electrical properties of copper
    nanowires by measuring temperature dependent
    electrical resistivity

9
Procedure
  • Determination of electrodeposition conditions
  • Form contiguous copper thin films without powdery
    deposits
  • Plated on Brass substrates with 99.9 copper as
    anode
  • Acid copper electrolyte
  • Direct Current and Pulse-reverse current tested
  • Selective chemical etching for grain size
    observation

10
Procedure
  • Electrodeposition of Copper nanowires
  • Anodization of Al to form alumina templates
  • A) clean and cut Al to appropriate size
  • B) Anodization of Al
  • 20V Al anode Platinum coated Titanium cathode
  • C) formation of hexagonally close packed Alumina
  • Average pore size 30nm
  • D), E) selective chemical etching
  • D) Aluminum backing
  • E) Barrier layer etching to open pores

11
Procedure
  • Electrodeposition of Copper nanowires
  • F) Sputter Au seed layer
  • To form working conductive electrode
  • G) Place templates on glass slide to form
    workable electrode
  • Copper tape and silver paint used to form
    electrical connection
  • H), I) electrodeposition of nanowires
  • Same electrolyte solution
  • J), K) Isolation of alumina template with
    enclosed nanowires
  • J) removal from glass slide through acetone
  • E) mechanical removal of gold seed layer
  • L) Chemical dissolution of alumina template

12
Grain Size versus Current Density
Increasing current
Grain size decreases as direct current is
increased. Agitation increases grain size.
13
Prelim. Grain Size Tests
Figure 3. Grain size was similar or slightly
decreased in reverse-forward plating as compared
to direct current plating
14
Prelim. Grain Size Tests
Figure 4. The efficacy was nearly 100 for most
of current density conditions.
15
Prelim. Dep. Rate Tests
Figure 5. The deposition rate seems to linearly
increase as a function of current density.
16
Alumina Templates
2 hours
3 hours
4 hours
Figure 8. alumina template cross sections, taken
after 2hours, 3hours, and 4 hours of oxidation.
(19, 44, 65 micrometers, respectively)
17
Alumina Templates
Figure 9. The thickness seems to linearly
increase as a function of time in oxidation.
18
Templates with enclosed nanowires
Nanowire deposition in custom alumina templates.
Processed nanowires from the same template.
19
Results-300nm thick nanowires
Copper nanowire, length 8.4 micrometers. Grown
under 20mA/cm2 forward 60mA/cm reverse
conditions
Copper nanowire, length 12.7 micrometers. Grown
under16mA/cm2 conditions.
20
Nanowire Lengths
Copper nanowire, diameter 30 nanometers. Grown
under 20mA/cm2 forward 60mA/cm reverse
conditions
Copper nanowire, diameter, 30 nanometers. Higher
resolution.
21
Future Plans
  • Further nanowires have been made with custom
    anodized alumina templates
  • sent to TEM for imaging and confirmation of
    nanotwin structure growth
  • If nanotwin structures within the nanowires are
    confirmed
  • further testing to find out the optimum current
    condition and other aspects will be done

22
Acknowledgement
  • I would like to thank
  • Dr. B.Y. Yoo
  • Dr. Nosang Myung
  • UCR NSF REU BRITE program
  • UCR Nano Electrochemical System Laboratory (NESL)
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