P. 3.1

1
Digital Technology and Computer Fundamentals

• Chapter 3
• Sequential Logic Circuits

2
Objectives

• At the end of this chapter, you should be able
  to
• define what is a sequential circuit
• draw the circuit diagram of an SR flip-flop and
  explain its function
• draw the circuit diagram of a JK flip-flop and
  explain its function
• explain the functions of D-type and T-type
  flip-flops

3
Objectives (Contd)

• differentiate the functions of triggering
  control
• identify the representations for different types
  of triggering in a circuit symbol
• explain the functions of direct inputs

4
Objectives (Contd)

• explain the operations of shift register
  circuits and
• explain the operations of the asynchronous and
  synchronous counter circuits.

5
References

• Thomas C. Bartee, "Digital Computer
  Fundamentals," sixth edition, McGraw-Hill
  Publishing Company.
• Richard S. Sandige, "Modern Digital Design,"
  McGraw-Hill Publishing Company.
• Theodore F. Bogart Jr., "Introduction to Digital
  Circuits," McGraw-Hill Publishing Company.

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Introduction

• Those whose outputs depend on the state of inputs
  and the previous state of the outputs.
• Able to remember a logic value.
• Several types of sequential logic circuits.
• flip-flops
• counters
• shift registers.

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Flip Flop

• A bi-stable element.
• Two stable states, 1 or 0.
• Able to store a digital value.
• Depends on the input and the previous value
  stored.
• Basic elements of a memory device in a digital
  computer.
• The outputs of Q and are complemented to each
  other.

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Flip Flop (Contd)

• To understand, one must be familiar with the
  functions of logic gates.
• NAND gate Output is 1 whenever there is a 0 at
  the inputs.
• NOR gate Output is 0 whenever there is a 1 at
  the inputs.

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Flip Flop (Contd)

• Propagation delay of the logic gates.
• Outputs of the logic gates take time to response
  to input changes.
• Outputs change in response to the change of
  inputs and The previous change of the outputs.
• Time required to settle to a stable state, i.e.
  the final values of outputs.

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Flip Flop (Contd)

• An initial value, 1 or 0, must be assigned to
  the previous outputs for deducing the final
  output values.
• We usually use the symbol Qn to denote the
  initial (or previous) value of the output and
  Qn1 to denote the new value of the stable
  output.

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S-R (Set-Reset) Flip Flop

• S-R flip-flop is the simplest one.
• Can be made by any logic gates.

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S-R Flip Flop (Contd)

• Case 1 S R 0.
• Assume Q 0 and 1.
• Substitute values into eq. 3.1 and 3.2
• New output values Q 0 and 1.
• If initially, Q 1 and 0
• New outputs are Q 1 and -Q 0.
• Conclusion outputs, Q and -Q, are unchanged if
  both inputs are 0.

13
S-R Flip Flop (Contd)

• Case 2 S 0, R 1.
• Assume Q 0 and -Q 1.
• Substitute values into eq. 3.1 and 3.2,
• New output values Q 0 and -Q 1.
• If Q 1 and -Q 0 are initial state
• New outputs Q 0 and -Q 0.
• Not a stable state.
• Subsequent changes are illustrated in timing
  table.

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S-R Flip Flop (Contd)

• Time sequence starts from left to right.
• Adjacent columns represent a time interval, the
  propagation delay.
• Output values at time tn determined by values of
  the gate inputs at time tn-1.

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S-R Flip Flop (Contd)

• The outputs Q and -Q settle at time t3.
• Their values are 0 and 1 respectively.
• Concluion The output Q is reset to 0 when the S
  is 0 and R is 1.

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S-R Flip Flop (Contd)

• Case 3 S 1 R 0.
• If initially, Q 0 and -Q 1.
• New output values are Q 0 and -Q 0.
• Analysis with the timing table required.

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S-R Flip Flop (Contd)

• Values of the Q and -Q settle at time t3
• Values are 1 and 0 respectively.
• If Q 1 and -Q 0 are the initial state
• New outputs are same Q 1 and -Q 0.
• Conclusion The output Q is set to 1 when the S
  is 1 and R is 0.

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S-R Flip Flop (Contd)

• Case 4 S 1 R 1.
• The outputs will be all 0 no matter what their
  initial values are.
• If then, the inputs are all reset to 0
• race happens between the logic gates.
• Which output is 1 cannot be determined.
• Conclusion this case should never happen in a
  practical circuit.

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S-R Flip Flop (Contd)

• Truth table of the S-R flip-flops
• Different circuits can be found from the same
  truth table.
• For example using NAND gates as in lecture notes.

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J-K Flip Flop

• Disadvantage of the S-R flip-flop only three
  cases of inputs are used.
• The J-K flip-flop is designed to overcome such
  limitation.

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J-K Flip Flop (Contd)
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J-K Flip Flop (Contd)
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J-K Flip Flop (Contd)

• Case 1 J 0 K 0.
• Outputs of the gates G1 and G2, will be 1
  regardless the values of Q and
• Conclusion Q and will remain unchanged.

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J-K Flip Flop (Contd)

• Case 2 J 0 K 1.
• Initially, Q is 0 and -Q is 1
• Substituting all the values into the Eq.3.3 to
  Eq.3.6
• The final values of G1, G2, Q and -Q are 1, 1, 0,
  and 1 respectively.

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J-K Flip Flop (Contd)

• Initially, Q is 1 and -Q is 0
• Analysis with the timing table required.

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J-K Flip Flop (Contd)

• Conclusion Outputs Q and -Q will be 0 and 1
  respectively regardless their initial values if
  the inputs J and K are 0 and 1 respectively.

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J-K Flip Flop (Contd)

• Case 3 J 1 K 0.
• Initially, Q is 0 and -Q is 1
• Substituting all the values into the Eq.3.3 to
  Eq.3.6
• Analysis with timing table

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J-K Flip Flop (Contd)

• The final values of G1, G2, Q and are 1, 1,
  1, and 0 respectively.

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J-K Flip Flop (Contd)

• Initially, Q is 1 and -Q is 0
• The stable values of G1, G2, Q and -Q are 1, 1,
  1, and 0 respectively.
• Conclusion Outputs Q and -Q will be 1 and 0
  respectively regardless their initial values if
  the inputs J and K are 1 and 0 respectively.

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J-K Flip Flop (Contd)

• Case 4 J 1 K 1.
• Analysis of this case must make use of the timing
  table.

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J-K Flip Flop (Contd)

• Setting both J and K inputs at 1 indefinitely
  will make the outputs change indefinitely.
• The real effect of such input change is to make
  the output change from 0 to 1 or from 1 to 0.

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J-K Flip Flop (Contd)

• Truth table of J-K flip-flops.

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Symbols of the S-R and J-K flip-flops

• Circuit symbols of basic flip-flops.

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D-type Flip-Flop

• Truth table and circuit symbol

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T-type Flip-Flop

• Truth table and circuit symbol

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Triggering of flip-flop

• With a timing diagram, we can forecast the
  behavior of a flip-flop

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Triggering of flip-flop (Contd)

• A flip-flop is triggered by the changes at its
  inputs.
• Such triggering has immediate effect on the
  output.
• Output will be out of control if unwanted
  situation happens
• Need certain control on this triggering.
• Use a clock signal.

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Clock Signal
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Triggering with Clock

• Level-triggered (clocked)
• A flip-flop responses to the input changes when
  the clock is at logical 1 is called a positive
  clocked (positive level-triggered) flip-flop.
• A negative clocked (negative level-triggered)
  flip-flop responses to the input changes when the
  clock is at logical 0.

40
Triggering with Clock (Contd)

• Edge-triggered
• A flip-flop responses to the input changes when
  the clock changes from logical 0 to logical 1 is
  called a positive edge-triggered flip-flop.
• A negative edge-triggered flip-flop responses to
  the input changes when the clock changes from
  logical 1 to logical 0.

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Positive clocked S-R Flip-Flop

• Truth table and circuit symbol

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An Example

• Waveform of a positive clocked SR FF

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Negative clocked D-type Flip-Flop

• Truth table and circuit symbol

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Positive edge-triggered T-type Flip-Flop

• Truth table and circuit symbol

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Negative edge-triggered J-K Flip-Flop

• Truth table and circuit symbol

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Another Example

• Waveform of a negative clocked JKFF

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More Example

• Waveform of a negative edge-triggered JK FF

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Direct inputs

• Direct inputs allow the users to assign the
  state of a flip-flop directly without going
  through the normal inputs.
• An example a negative edge-triggered J-K
  flip-flop with direct preset and clear inputs.
• Q will be set to logical 1 if PS, preset, is 0.
  If Clr, clear, is 0, Q output will be reset to 0,
  i.e. Low activated.