Lattice Verilog Training

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Lattice Verilog Training

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Part I Jimmy Gao Verilog Basic Modeling Structure Verilog Design Description Verilog language describes a digital system as a set of modules module counter ... – PowerPoint PPT presentation

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Title: Lattice Verilog Training

1

Lattice Verilog Training
Part I
Jimmy Gao

Verilog
Basic Modeling Structure

3
Verilog Design Description

Verilog language describes a digital system as a
set of modules
module counter() module module_name
(port_list)
declares
endmodule module_items
module t_ff() endmodule
... ...
endmodule
module dff()
endmodule
module inv()
endmodule

Ripple Carry Counter
T_FF (tff0)
T_FF (tff1)
T_FF (tff2)
T_FF (tff3)
DFF
INV
DFF
INV
DFF
INV
DFF
INV
4
The Black Box Example

Verilog description of the black box
module black_box(Rst, Clk, D, Q, CO)
input Rst, Clk
input70 D
output CO
output70 Q
endmodule

5
Simple Verilog Example
module logic ( a, b, w, x, y, z) //
Module name Port list // Declaration
section input a, b output x,
y, z output 30 w //
Module Items // Continuous Assignment assign
z a b // XOR assign y a b //
AND assign x 1b1 assign w
4b1010 endmodule
Describe Design I/Os
a
z
b
y
x
1b1
w
4b1010
Describe Design Content
6
Verilog Design Description

The module_name is an identifier of the modules
The port_list is a list of input, output and
inout ports which are used to connect to other
modules
The declares section specifies the type of data
objects (input, output, inout, regs, wires etc)
and procedural constructs (functions and tasks)
The module_items may be
always constructs gt behavioral modeling
continuous assignments gt data flow modeling
instantiation of modules gt structural modeling
REMEMBER
The identifiers in Verilog are case-sensitive
and all keywords must be in lower-case

7
DECLARATIONS

External Ports
input A signal that goes into the module
output A signal that goes out of the module
inout A signal that is bi-directional (goes into
and out of the module
Internal Data Objects
wire A net without storage capacity
reg can store the last value assigned physical
data type not a hardware register yet
integer
real other register type declaration abstract
data type
time

8
DECLARATIONS

Declaration Format
Class Width Data-Object Example
input 40 a 5b10001
inout b 1b1
output 30 c 4hF
reg 02 d 3b001
wire e 1b0
integer f -40
real g 3.12
time h 6

Physical Data Type
Abstract Data Type
timescale 1ns / 0.1ns time h assign h 6
6ns
9
Data Types

Physical Data Types (for reg and wire)
0 logical zero or false
1 logical one or true
x unknown logical value
z high impedance of tristate gate
Abstract Data Types
integer a general purpose 32-bit variable
real a real number (no range declaration)
time units for simulation time

10
Number Specification

Sized Number
4b1010 // 4-bit binary number 1010
12hafd // 12-bit hexadecimal number afd
16d225 // 16-bit decimal number 225
Unsized Number
23456 // 32-bit decimal number
hc3 // 32-bit hexadecimal number
o21 // 32-bit octal number
X or Z value
6hx // 6-bit hex number
32bz // 32-bit high impedance number

11
Number Specification

wire 70 bus
bus 8b10101010 bus 8bz
bus 8hFF bus 8hx
reg reset
reset 1b1
integer counter
counter -1 counter hA
real delta
delta 4e10

Verilog Language Syntax
Verilog Design Methods

13
Structure of Verilog Module
module Name ( Port list )
Declaration Sections
Port declaration Wire, Regs declaration etc.
Module Items
Continuous Assignments Data Flow Modeling
Instantiation of lower level modules Structural
Modeling
Always blocks Behavioral Modeling
endmodule
14
Structural Modeling
module one_bit_full_adder ( sum, cout, a, b, cin
) // Declaration section input a, b,
cin output sum, cout wire s1, s2,
c1 // Structural Modeling Method - Instantiation
of modules XOR2 X1(.Z0(s1), .A0(a), .A1(b))
AND2 A1(.Z0(c1), .A0(a), .A1(b)) XOR2
O1(.Z0(cout), .A0(s2), .A1(c1)) XOR2 X2(sum,
s1, cin) AND2 A2(s2, s1, cin) endmodule
Library Symbol AND2
A0
Z0
A1
module AND2 (Z0, A0, A1) input A0, A1 output
Z0 endmodule
a
s1
sum
X1
b
X2
c1
s2
A0
cout
A1
A2
O1
Z0
A1
AND2
cin
15
Verilog Exercise 1
Complete the instantiation statements in
following structural Verilog design. Use name
association for the first one and positional
association for the second. module design
(data_in, clock, clear, out_enable, data_out)
input data_in, clock, clear, out_enable
output data_out wire q FD21 dff1 (
) // Name Association OT11 obuf1 (
) // Position Association endmodule
out_enable
module OT11(XO0,A0,OE) input A0, OE output
XO0 endmodule
oe
q
D0
Q0
data_in
XO0
A0
data_out
CLK
CD
clock
OT11
FD21
clear
16
Verilog Exercise 1 - Answer
module design (data_in, clock, clear,
out_enable, data_out) input data_in,
clock, clear, out_enable output data_out
wire q // Name Association FD21 dff1
(.D0(data_in), .Q0(q), .CLK(clock), .CD(clear))
// Position Association OT11 obuf1 (
data_out, q, out_enable ) endmodule
out_enable
module OT11(XO0,A0,OE) input A0, OE output
XO0 endmodule
oe
q
D0
Q0
data_in
XO0
A0
data_out
CLK
CD
clock
OT11
FD21
clear
17
Data Flow Modeling - Continuous Assignment

Continuous assignment
Use assign key word Execute concurrently
assign out i1 i2 // AND
assign addr150 addr1_bits150
addr2_bits150 // XOR
Implicit Continuous Assignment
// Regular continuous assignment
wire out
assign out in1 in2
// Implicit continuous assignment
wire out in1 in2
Continuous Assignment with conditional operator
assign x y ? b a b

NOTE Variable (Test Condition) ? (True logic)
(False Logic)
18
Continuous Assignment Format

Assign (keyword) Logical Expression
assign out a b
Left operand Right operands operator

19
Conditional Continuous Assignment Format

Assign (keyword) Conditional Logical
Expression
assign target condition ? 1st-Expression
2nd-Expression
If condition is TRUE or One, target
1st-Expression
If condition is FALSE or Zero, target
2nd-Expression.
Ex x y ? a b c m - n - p
if y 1b1, x a b
c
if y 1b0, x m - n -
p

20
Operators

Binary Arithmetic Operators operate on two
operands
Operator Name Comments
Addition
- Subtraction
Multiplication
/ Division divide by zero produces an x.
Modulus
Logical Operators operate on logical operands and
return a logical value
Operator Name
! Logical Negation
Logical AND
Logical OR

21
Operators

Relational Operators compare two operands and
return a logical value.
Operator Name Comments
gt Greater than
lt Less than
gt Greater than or equal to
lt Less than or equal to
Equality Operators compare two operands and
return a logical value.
Operator Name Comments
Equality result unknown if including x or z
! Inequality result unknown if including x or
z
Case Equality equal including x or z
! Case Inequality unequal including x or z

22
Operators

Bitwise Operators operate on the bits of operands
Operator Name
Bitwise negation
Bitwise AND
Bitwise OR
Bitwise XOR
Bitwise NAND
Bitwise NOR
or Bitwise NOT XOR

23
Operators Examples

Example a 4b1000 b4b0111
(1) a b 4b0000
a b 4b1111
(2) a - b 4b1000 - 4b0111 4b0001
8 - 7 1
(3) a gt b compare 4b1000 gt 4b0111 TRUE
a b compare 4b1000 4b0111 FALSE
(4) !(a gt b ) !(TRUE) FALSE
( a gt b ) ( a b ) TRUE FALSE
TRUE

1000 0111 0000
Bitwise AND
1000 0111 1111
Bitwise XOR
24
Operators

Shift Operators
Operator Name
ltlt Shift Left
gtgt Shift Right
// A 4b1010
Y A ltlt 1 // Y 4b0100
Y A gtgt 2 // Y 4b0010
Concatenation Operator ,
// A 2b00 B 2b10
Y A, B // Y 4b0010
Y 2A, 3B // Y 10b0000101010

Add Zero at the end while left shifting
Add Zero at the beginning while right shifting
25
Data Flow Modeling Example
module one_bit_full_adder ( sum, cout, a, b, cin
) // Declaration section input a, b,
cin output sum, cout wire s1, s2,
c1 // Structural Modeling Method - Continuous
Statement assign s1 a b assign c1 a
b assign sum s1 cin assign s2 s1
cin assign cout s2 cin endmodule
a
s1
sum
b
c1
s2
cout
cin
26
Verilog Exercise 2
Please Complete the following Design in Data-Flow
Modeling Method by using concurrent conditional
assignment. module four_to_one_mux ( a, b, c, d,
s0, s1, o ) // Declaration section input a,
b, c, d, s0, s1 output o wire m0,
m1 // Module Items in Data-Flow Modeling
Method endmodule
s1
a
m0
b
o
s0
c
m1
d
27
Verilog Exercise 2 - Answer
module four_to_one_mux ( a, b, c, d, s0, s1, o
) // Declaration section input a, b, c, d,
s0, s1 output o wire m0, m1 //
Structural Modeling Method - Continuous
Statement assign m0 s0 ? a b assign m1 s0
? c d assign o s1 ? m0 m1 // assign o
s1 ? ( s0 ? a b) ( s0 ? c d) endmodule
s1
a
m0
b
o
s0
c
m1
d
28
Behavioral Modeling

always Block
Basic Structured Procedure in behavioral
modeling
All other behavioral statements can appear only
inside the
always Block
Timing Control
Event Based Timing Control _at_
Procedural Assignments
Blocking Assignment (sequential)
Non-Blocking Assignment (concurrent) lt
Conditional Statement
If-Else Statement
Multi-way Branching
Case Statement

29
always block with Event-Based Timing Control

The syntax of an always block is
always _at_ (event or event or ...)
begin
statement1
statement2
statementN
statementN1
end
Statements can be executed when the specified
event
occurs.
A always block is generally used to implement
latches
or flip-flops.

Each statement executes sequentially
30
always block

Simple example of always
reg q
always _at_(posedge clk) // the sensitivity list
begin
q d // define the always block
end
Here the signal q is sensitive to a rising edge
on signal clk. Whenever the condition is met,
the statement inside the process will be
evaluated
q is declared as reg type and q is sensitive
to a rising edge. Therefore q becomes a
hardware register.

q
d
clk
31
always block vs. continuous assignment

Another example of always
input a, b, s out x reg x
always _at_(a or b or s) // Behavioral Modeling
begin
if ( !s ) x a
else x b Process activates when any
of these
end signals change state
x is declared as reg type but x is sensitive
to level changes of signal a, b, s.
Therefore x is not hardware register.
This example also can be implemented by using
assign statement
assign x s ? b a // Data Flow Modeling

s
a
x
b
32
Procedural Assignments - Blocking Assignments

Procedural assignments - Blocking Assignments
Procedural blocking assignments are sequential
Statements inside the block execute in sequence,
one after another.
Example
// breg, creg, dreg are related.
reg breg, creg, dreg
always _at_( posedge clk )
begin
breg areg
creg breg
dreg creg
end

breg
areg
creg
clk
dreg
33
Procedural Assignments - Non-Blocking Assignments

Procedural assignments - Non-Blocking Assignments
Procedural Non-blocking assignments are
concurrent Statements inside the block execute
right at the same time.
Example
// breg, creg, dreg are related.
reg breg, creg, dreg
always ( posedge clk )
begin
breg lt areg
creg lt breg
dreg lt creg
end

breg
creg
dreg
areg
clk
34
Blocking Assignments vs. Non-Blocking Assignments

always _at_( a )
begin
10 b a // AT TIME UNIT 10
10 c b // AT TIME UNIT 20
10 d c // AT TIME UNIT 30
10 o d // AT TIME UNIT 40
end
always _at_( a )
begin
10 b lt a // AT TIME UNIT 10
10 c lt b // AT TIME UNIT 10
10 d lt c // AT TIME UNIT 10
10 o lt d // AT TIME UNIT 10
end

35
Procedural Assignments - Blocking/Non-Blocking
Assignments

module regs (a, b, c, clk, q1, q2, q3)
output q1, q2, q3 input a, b, c, clk reg q1,
q2, q3
always _at_( posedge clk )
begin
q1 a
q2 b
q3 c
end endmodule
module regs (a, b, c, clk, q1, q2, q3)
output q1, q2, q3 input a, b, c, clk reg q1,
q2, q3
always _at_( posedge clk )
begin
q1 lt a
q2 lt b
q3 lt c
end endmodule

a
q1
clk
b
q1 a
q2
q2 a
clk
c
q3 a
q3
clk

t
t
a
q1
clk
b
q1 a
q2
q2 a
clk
c
q3 a
q3
clk

36
Procedural Assignment Format

always _at_ ( sensitive event list )
begin
// Procedural Assignments
xyz lt m n // non-blocking assignment
out a b // blocking assignment
Logical Expression
xyz lt m
n
out a b
Left operand Right operands operator
end

37
Continuous Asign. vs. Procedural Blocking Assign.

module design ( . )
..
// Continuous Assignments
// Statements are executed concurrently
assign sum a b
assign z x y
always _at_ ( sensitive event list )
begin
.
// Procedural Blocking Assignments
// Statements are executed sequentially
w m n
k p q
end
endmodule

The Statements inside the always block as a whole
is executed concurrently
38
Conditional Statements -- if - else

Conditional Statements -- if ... else
if ... else statements execute a block of
statements according to the value of one or
more expressions.
if (expressions)
begin
... statements ...
end
else statement-block
begin
... statements ...
end
if ( expressions ) single statement A
else if ( expression ) single statement B
else single statement C

39
Multi-way Branching -- case

Multi-way Branching -case
case statement is a special multi-way decision
statement that tests whether an expression
matches one of the other expressions, and
branches accordingly
reg10 rega
reg30 result
... ...
case (rega)
2b00 result 4b0000
2b01 result 4b0001
2b10 result 4b1000
default result 4b1111
endcase

40
Verilog Review

module Example (a, b, c, d, s, o )
// port declaration section
input a, b, c, d, s
output o
// wire reg declaration section
wire m0, m1
reg temp1, temp2, o
// continuous assignment
assign m0 a b
// instantiation statement
AND2 A1(.Z0( m1 ), .A0( c ), .A1( d ))
// always block
always _at_(m0 or m1 or s)
begin
temp1 m0
temp2 m1

s
a
m0
b
o
c
m1
d
statements outside always block executed currently
always block as a whole is executed concurrently
Statements inside always block executed
sequentially
41
Verilog Exercise 3

What kind of hardware function is composed by the
following Verilog design?
What is wrong with the following Verilog design
code?
Can you re-write the Verilog code by using
if-then-else statement?

42
Verilog Exercise 3

Module design (out, a, b, c, d, s0, s1)
input a, b, c, d, s0, s1
output out
always
case ( s1, s0 )
2b00 out a
2b01 out b
2b10 out c
2b11 out d
endcase
endmodule

43
Verilog Exercise 3 - Answer

Module design (out, a, b, c, d, s0, s1)
input a, b, c, d, s0, s1
output out
reg out
// left-hand value inside the always
// statement must retain value. Therefore
// out must be reg type. But out is
// not hardware register.
always _at_(a or b or c or d or s0 or s1) //
Sensitive List
case ( s1, s0 )
2b00 out a
2b01 out b
2b10 out c
2b11 out d
endcase
endmodule

a
b
out
c
d
s0
s1
44
Verilog Exercise 3 - Answer

module mux4_to_1 (out, a, b, c, d, s0, s1)
input a, b, c, d, s0, s1
output out
reg out
// left-hand value inside the always
// statement must retain value. Therefore
// out must be reg type. But out is
// not hardware register.
always _at_(a or b or c or d or s0 or s1) //
Sensitive List
if ( s0, s1 2b00 )
out a
else if ( s0, s1 2b01 )
out b
else if ( s0, s1 2b10 )
out c
else
out d
end

a
b
out
c
d
s0
s1
45

Lab One - Combinatorial Logic
Please Turn to your Verilog Lab Book for the
Verilog Design Lab No. One

Understand Verilog Synthesis
Verilog Design Application

47
Registers in Verilog

Registers -- declarations and triggers
declares
input clk, x_in
input data1, data2, data3
input 40 q_in
reg x // single bit
reg a, b, c // three single-bit registers
reg40 q // a 5-bit vector
triggers
always _at_(posedge clk) begin
q q_in
end
always _at_(negedge clk) begin
x x_in
a data1

q_in
q
1
clk
0
x_in
x
clk
1
0
48
Registers in Verilog -- asynchronous reset

Registers -- Asynchronous Reset
module async_reset(d, clk, rst, q)
input d, clk, rst
output q
reg q
always _at_(posedge clk or posedge rst)
begin
if (rst)
q 0 // asynchronous reset
else
if ( clk )
q d
end
endmodule

d
q
clk
rst
49
Registers in Verilog -- synchronous reset

Registers -- synchronous Reset
module sync_reset(d, clk, rst, q)
input d, clk, rst
output q
reg q
always _at_(posedge clk)
begin
if (clk)
begin
if ( rst )
q 0 // synchronous reset
else
q d
end
end
endmodule

rst
d
q
1b0
clk
50
Registers in Verilog -- Short Format

Register -- synchronous Reset
module sync_reset(d, clk, rst, q)
input d, clk, rst output q reg q
always _at_(posedge clk)
if ( rst )
q 0 // synchronous reset
else
q d
endmodule
Register -- Asynchronous Reset
module asyn_reset(d, clk, rst, q)
input d, clk, rst output q reg q
always _at_(posedge clk or posedge rst)
if ( rst )
q 0 // asynchronous reset
else
q d
endmodule

rst
d
q
1b0
clk
q
d
clk
rst
51
Asynchronous Reset Counter

module counter(clock,asy_reset,count)
input clock, asy_reset
output 03 count
reg 03 count
always _at_ ( posedge clock or posedge asy_reset )
begin
if ( asy_reset )
count 4b0000
else begin
if (clock) count count
4b0001
end
end
endmodule

count
clock
count
asy_reset
52
Synchronous Reset Counter

module counter(clock,syn_reset,count)
input clock, syn_reset
output 03 count
reg 03 count
always _at_ ( posedge clock )
begin
if ( clock )
begin
if ( syn_reset )
count 4b0000
else
count count 4b0001
end
end
endmodule

count
clock
count
syn_reset
53
Latches in Verilog -- asynchronous reset

Latches -- asynchronous Reset
module async_reset_dlatch(d, enable, rst, q)
input d, enable, rst
output q
reg q
always _at_(enable or rst or d )
begin
if (rst)
q 0 // asynchronous reset
else
begin
if ( enable )
q d
end
end
endmodule

d
q
enable
rst
54
Latches in Verilog -- synchronous reset

Latches -- synchronous Reset
module sync_reset_dlatch(d, enable, rst, q)
input d, enable, rst
output q
reg q
always _at_(enable or d )
begin
if (enable)
begin
if ( rst )
q 0 // synchronous reset
else
q d
end
end
endmodule

rst
d
q
1b0
enable
55
asynchronous/synchronous reset(contd)

Latches -- asynchronous Reset
module async_reset_dlatch(d, enable, Rst, Q)
input d, enable, Rst
output Q
// asynchronous reset D_Latch
assign Q Rst ? 0 ( enable ? d Q )
// wire Q Rst ? 0 ( enable ? d Q )
endmodule
Latches -- synchronous Reset
module sync_reset_dlatch(d, enable, Rst, Q)
input d, enable, Rst
output Q
// synchronous reset D_Latch
assign Q enable ? ( Rst ? 0 d ) Q
// wire Q enable ? ( Rst ? 0 d ) Q
endmodule

56
Output Enable

Example 1
module oe1(data, data_in, enable)
output data
input data_in, enable
reg data
always _at_(enable)
if(enable) data data_in
else data 1bz
endmodule
Example 2
module oe2(data, data_in, enable)
output data
input data_in, enable
assign data enable ? data_in 1bz
endmodule
Example 3
module oe3(data, data_in, enable)

enable
data
data_in
57
Bi-Directional Port

Example 1
module bi-port1(data, data_in, enable, fb)
inout data
input data_in, enable
output fb
assign data enable ? data_in 1bz
assign fb data
endmodule
Example 2
module bi-port2(data, data_in, enable, fb)
inout data
input data_in, enable
output fb
wire data enable ? data_in 1bz
wire fb data
endmodule

enable
data_in
data
fb
58
Implicit Synthesis Result Excluding else
implies latch

Implied memory (latch) will occur if future value
of signal cannot be determined
if-else statement
always _at_(a or b) begin
if (a)
begin
step b
end
end
The signal will keep the previous value in this
case
A latch may also be created by using case
statement
Specify all conditions to avoid implied latch

59
Verilog Exercise 4

The following Verilog Design is a 4-bit counter
with Asynchronous Reset, Synchronous Preset and
Synchronous Load. Please fill in the blank
section of the Verilog source code to complete
the design.

60
Verilog Exercise 4

module counter(clock,asy_reset,syn_preset,syn_load
,data_in,count)
input clock, asy_reset, syn_preset,
syn_load
input 03 data_in
output 03 count
reg 03 count
always _at_ ( )
begin
if ( )
count 4b0000
else begin
if (clock) begin
if ( )
count 4b1111
else if ( )
count data_in
else
count count 4b0001
end
end

61
Verilog Exercise 4 - Answer

module counter(clock,asy_reset,syn_preset,syn_load
,data_in,count)
input clock, asy_reset, syn_preset,
syn_load
input 03 data_in
output 03 count
reg 03 count
always _at_(posedge clock or posedge asy_reset)
begin
if (asy_reset 1b1)
count 4b0000
else begin
if (clock) begin
if ( syn_preset )
count 4b1111
else if ( syn_load )
count data_in
else
count count 4b0001
end
end

Verilog Hierarchical Design

63
Hierarchy Designs

Advantages
Allows duplication of common building blocks
Components (Verilog modules) can be created,
tested and held for use later
Smaller components can be more easily integrated
with other blocks
Designs become more readable
Designs become more portable
The design task can be split among several
members of a team

64
Hierarchy Designs (cont.)

Design example
module addmult(op1, op2, result)
input20 op1, op2
output30 result
wire30 s_add component declaration
add adder(op1, op2, s_add)
name of lower level component
assign result s_add - 2b10
endmodule
module add(in1, in2, out1) // lower level
component add
input20 in1, in2
output30 out1

addmult
add
op1
in1 in2
s_add
out1
result
op2
2b10
65
Hierarchy Designs (cont.)

Lower level design can be in the same file as the
top-level design (above example) or in a separate
file with a user defined file name
include add.v // include File add.v.
// This Format is not needed for Synplicity.
module addmult(op1, op2, result)
input20 op1, op2
output30 result
wire30 s_add
add adder(op1, op2, s_add)
assign result s_add - 2
endmodule
Important!!! A is NOT the same as a . See
include above!