EGR 277 Digital Logic

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Lab 2 EGR 270 Fundamentals of Computer
Engineering
EGR 270 Fundamentals of Computer Engineering Lab
2 Logic Gate Characteristics

• Related documents for Lab 2
• Lab 2
• Capturing Oscilloscope Images Using WaveStar
• 7400 Data Sheet
• Downloading Data Sheets from the Internet

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Lab 2 EGR 270 Fundamentals of Computer
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Logic Gate Characteristics The physical
characteristics of logic gates often play an
important role in the design of digital circuits.
This lab focuses on several of these
characteristics, including

• voltage and current levels
• noise margin
• fanout and loading
• propagation delay
• Each of these physical characteristics are
  discussed below.
•  
• Current Direction
• According to IEEE standards, currents are
  directed into devices.
• Therefore,
• if a current in a specification is positive, it
  is entering the device.
• if a current in a specification if negative, it
  is leaving the device.

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Lab 2 EGR 270 Fundamentals of Computer
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• Voltage and Current Levels
• Several voltage and current levels are of
  interest when working
• with logic gates, including
• VOL output voltage when the gate is LOW
• VOH output voltage when the gate is HIGH
• VIL input voltage when the gate is LOW
• VIH input voltage when the gate is HIGH
• IOL output current when the gate is LOW
• IOH output current when the gate is HIGH
• IIL input current when the gate is LOW
• IIH input current when the gate is HIGH

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Lab 2 EGR 270 Fundamentals of Computer
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7400 Voltage and Current Specifications
Refer to the data sheet for the 7400 Quad 2-input
NAND (see next slide or instructors web page)
and fill out the table shown.
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Lab 2 EGR 270 Fundamentals of Computer
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7400 Data Sheet (selected sections)
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Lab 2 EGR 270 Fundamentals of Computer
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7400 Data Sheet (selected sections)
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Lab 2 EGR 270 Fundamentals of Computer
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Noise Margins VOL(max) is lower than VIL(max) to
allow for noise and signal deterioration.
Similarly VOH(min) is higher than VIH(min).
These differences in voltages are referred to as
noise margins. Defined more exactly VNL LOW
level noise margin VIL(max) - VOL(max) VNH
HIGH level noise margin VOH(min) -
VIH(min) Example Find the noise margins for
standard TTL devices (fill in the blanks) VNL
VIL(max) - VOL(max) _____ - _____
_____ VNH VOH(min) - VIH(min) _____ -
_____ _____
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Lab 2 EGR 270 Fundamentals of Computer
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Noise Margins - TTL noise margins are
illustrated below.
Example Sketch an example of a noisy signal
below
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Lab 2 EGR 270 Fundamentals of Computer
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Fanout Fanout is the number of standard loads
that the output can drive. For TTL devices, the
number of standard loads is limited by the amount
of input current each load requires as compared
to the current that the driving gate can deliver.
Fanout, therefore, is generally considered to be
the smaller of the following two items
Example Find the fanout for standard TTL
devices
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Lab 2 EGR 270 Fundamentals of Computer
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Fanout - Illustration for a LOW TTL output
Fanout - Illustration for a HIGH TTL output
(draw in class)
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Lab 2 EGR 270 Fundamentals of Computer
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• Fanout for CMOS devices
• Although we will not be testing CMOS devices in
  Lab 2, it is worth noting that fanout is much
  higher for CMOS devices than for TTL devices.
• IIL and IIH are extremely small for CMOS devices
  (lt 1 uA).
• Calculating fanout as we did for TTL devices
  might yield a fanout of 4000 for CMOS, compared
  to 10 for standard TTL!
• However, the input capacitance of CMOS gates
  affects propagation delay, so increased fanout
  results in increased delay.

• Summary
• Exceeding fanout specifications in TTL devices
  may result in excessive output current and may
  destroy the devices.
• Increased fanout in CMOS devices is primarily a
  problem in that it increases propagation delay.

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Lab 2 EGR 270 Fundamentals of Computer
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Propagation Delay Propagation delay is the time
that it takes a gate to switch logic levels.
Logic gates often have a different propagation
delay switching from LOW to HIGH than from HIGH
to LOW, so two types of delay are defined tPLH
propagation delay when the OUTPUT switches
from LOW to HIGH tPHL propagation delay when
the OUTPUT switches from HIGH to LOW tD the
maximum of tPHL and tPLH
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Lab 2 EGR 270 Fundamentals of Computer
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Propagation Delay - Illustration
Example Find the propagation delay for a 7400
2-input NAND
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Lab 2 EGR 270 Fundamentals of Computer
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Propagation Delay Oscilloscope
measurement Propagation delay for TTL gates will
be measured in Lab 2 using an oscilloscope. The
oscilloscope images can be captured using the
program WaveStar. The example shown below
represents the input and the output of an
inverter.
Discuss the image. Which delay is being
measured? a) tPHL b) tPLH What is the
delay? Label the voltage levels.
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Lab 2 EGR 270 Fundamentals of Computer
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Propagation Delay CMOS gates As discussed
earlier, fanout affects propagation delay for
CMOS gates. The table below from the text will
be discussed in more detail later in the course,
but note that the delay (in ns) for a 2-input
NAND is tD 0.05 0.014SL, where SL is the
number of standard loads.
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Lab 2 EGR 270 Fundamentals of Computer
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Propagation Delay CMOS gates Calculate the
propagation delay in each case for the CMOS gates
shown below. Recall that tD 0.05 0.014SL
for 2-input NANDs (in ns).
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Lab 2 EGR 270 Fundamentals of Computer
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• TTL Outputs
• TTL logic circuits typically have one of two
  types of outputs
• Totem-pole outputs (most common)
• Open-collector outputs
• Many TTL logic devices are available with either
  type of output.
• Examples
• 7400 Quad 2-input NAND (totem-pole outputs)
• 7401 Quad 2-input NAND (open-collector outputs)
• 7404 Hex Inverter (totem-pole outputs)
• 7405 Hex Inverter (open-collector outputs)
• 74155 Dual 2x4 Decoder (totem-pole outputs)
• 74156 Dual 2x4 Decoder (open-collector outputs)

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Lab 2 EGR 270 Fundamentals of Computer
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• TTL Totem-pole Outputs
• Shown below Internal circuitry of a 7400 2-input
  NAND (totem-pole outputs).
• The transistors (denoted by Q) essentially act
  like switches.
• Q4 stacked on top of Q3 forms the totem pole.
• Closed switch - transistor is ON. Open switch -
  transistor is OFF.
• HIGH output Q4 is ON, Q3 if OFF, and IOH flows
  through Q4 and out Y.
• LOW output Q4 is OFF, Q3 if ON, and IOL flows
  in Y and through Q3.

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Lab 2 EGR 270 Fundamentals of Computer
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• TTL Open-collector Outputs
• Shown below Internal circuitry of a 7401
  2-input NAND (open-collector).
• TTL circuits with open-collector outputs have
  only the lower transistor (Q3) seen in the
  previous totem-pole output.
• Since there is no internal path from the output Y
  to the supply voltage VCC , the circuit does not
  function properly unless an external pull-up
  resistor is used.

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Lab 2 EGR 270 Fundamentals of Computer
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TTL Outputs

• Totem-pole outputs
• No pull-up resistor needed
• Fixed 0V/5V output

• Open-collector outputs
• Pull-up resistor required
• Wide range of output HIGH voltages possible (up
  to 30V typically)

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Applications of open-collector gates Gates with
totem-pole outputs are simpler to use since they
require no external resistor. However, there are
three cases where open-collector gates are
useful 1) Wired-ANDing - Open-collector outputs
can be tied directly together which results in
the logical ANDing of the outputs. Thus the
equivalent of an AND gate can be formed by simply
connecting the outputs. This is especially
convenient when large numbers of signals need to
be ANDed. (Note that connecting the outputs of
totem-pole gates will typically destroy
them.) 2) Increased current levels - Standard TTL
gates with totem-pole outputs can only provide a
HIGH current output of 0.4 mA and a LOW current
of 1.6 mA. Many open-collector gates have
increased current ratings (30 mA to 40 mA
typically). 3) Different voltage levels - A wide
variety of output HIGH voltages can be achieved
using open-collector gates. This is useful in
interfacing different logic families that have
different voltage and current level requirements.

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Lab 2 EGR 270 Fundamentals of Computer
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Pull-up resistor calculations Many texts
recommend using pull-up resistors of 1k? or 2.2
k?. Values in this range are often sufficient,
but actually max and min values can be calculated
based on the number of gates as shown below.
Calculation for RP(max) Example Using M
4 and N 3 as shown on the left and using
standard TTL specifications
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Lab 2 EGR 270 Fundamentals of Computer
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Pull-up resistor calculations continued
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Lab 2 EGR 270 Fundamentals of Computer
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• Driving high-current loads using open-collector
  gates
• Open-collector gates gain to used to drive loads
  that require higher voltage and current levels,
  such as incandescent lamps and relays.
• Example open-collector gate 7406 Hex Inverter
  Buffer/Driver.
• IOL (max) 40 mA (instead of 16 mA)
• VOH(max) 30 V (instead of around 5V).
• The term driver typically indicates that a
  device provides higher output currents.

Example Use a 7406 inverter to drive an
incandescent lamp that requires a 12 V supply and
about 35 mA of current. Note that a
current-limiting resistor Rlimit may or may not
be necessary, depending on the resistance of the
lamp filament. The bulb lights when the gate
output is LOW.
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Lab 2 EGR 270 Fundamentals of Computer
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• Driving high-current loads using transistors
• Transistors can be used when open-collector
  outputs cant provide enough current.
• The transistor cats like a switch, where the
  switch is closed when the output of a logic gate
  is HIGH.
• Note the current limitations of the following
  devices

Example Use a 7406 and a transistor to run a
motor requires a 12 V supply and about 1 A of
current.
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Lab 2 EGR 270 Fundamentals of Computer
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• Logic Probes - Very handy devices for
  troubleshooting digital circuits.
• Switches
• TTL/CMOS pick the appropriate type of
  technology (TTL for Lab 2)
• NORMAL/PULSE use NORMAL for constant logic
  levels (Lab 2) and PULSE for cases where you want
  to detect a very brief pulse.
• Operation
• Connect alligator clips to power strips (5V and
  ground)
• If probe tip touches HIGH pin on IC, RED light
  turns on and buzzer sounds.
• If probe tip touches LOW pin on IC, GREEN light
  turns on and different buzzer sounds.