ISSCC 2003 Technical Program Status

1
ISSCC 2003 Technical Program Status
Anantha Chandrakasan 2003 Technical Program
Committee Chair
SSCS Adcom, August 26th, San Francisco
2
Plenary Speakers

• US Speaker
• Dr. Gordon Moore, IntelNo Exponential is
  Forever
• Far-east Speaker
• Prof. Takayasu Sakurai, University of Tokyo
  Perspective of Power-Aware Electronics
• European Speaker
• Bruno Murari, ST Microelectronics Groups
  (Vice president Telecoms Peripheral and
  Automotive Groups Director - RD)
• The Interface of the Electronic System to the
  External World the New Challenge for the Future

3
Three Evening Special Topic Sessions(All on
Sunday Night)

• WirelessHow Far Can Integration Go for 3G
  Cellphones?
• System Requirements and Integration Trends,
  Sven Mattisson, Ericsson
• Integration Of Analog, Digital and Power
  Regulation on a Chip, James Mielke, Motorola
• Advanced RF Integration, William Krenik, TI
• Challenges and Future Trends, John Long, Delft
  University of Technology
• Digital Circuits in Emerging Technologies
• CMOS High-Speed Broadband Techniques, M. Green,
  University of California, Irvine
• Design of SiGe bipolar circuits for 40 Gb/s
  applications, H. Knapp, Infineon
• Indium Phosphide Bipolar Integrated Circuits 40
  GHz and beyond, M. Rodwell, UCSB
• The Double-Gate FinFET Device Impact On Circuit
  Design, I. Aller, IBM
• Carbon nanotube field effect transistors and
  circuits, TBD
• Signal Processing Highlights of DAC
• Challenges in Achieving First-Silicon Success
  for 10M-Gate SoCs A Silicon Engineering
  Perspective Aurangzeb Khan, Simplex Solutions
  Inc.
• A Universal Technique for Fast and Flexible
  Instruction-Set Architecture Simulation Achim
  Nohl, Univ. of Technology, Aachen
• Fast and Accurate Behavioral Simulation of
  Fractional-N Frequency Synthesizers and other
  PLL/DLL Circuits Michael Perrott, MIT
• An Efficient Optimization-Based Technique to
  Generate Polynomial Performance Models for Analog
  Integrated Circuits Walter Daems, Katholieke
  Univ., Leuven

4
Six Evening Panels (reduced from 8 last year)

• Europe "Analog IP Stairway to SoC heaven?
• Far East Future mobile phones a beautiful
  dream or smoke in LSI technology?
• Analog SoC DOA? RIP?
• Imagers, Displays MEMS Will MEMS, Imagers,
  and Displays Be Key to the Growth of the IC
  Industry?
• Memory Good,Bad,Ugly- 50 Years of Evolution?
  What Next?
• Wireline Fineline Prototyping Breaking New
  Ground or Breaking the Bank?"

5
7 Tutorials

• Analog Basics of Serial Backplane Transceivers,
  Aaron Buchwald, Broadcom
• Wireless Highly Integrated RF Wireless
  transceivers, Tony Montalvo, Analog Devices
• Wireline DSL Splitters and Drivers, Elve Moons,
  Alactel Bell
• Digital Design for Test and Debug, Shannon
  Morton, Silicon Graphics
• Imagers, DISPLAYS and MEMS Introduction to
  BioMEMs and Nanobiotechnology, Dennis Polla
• Memory MRAM Technology Circuits, James
  Daughton NVE Corp.
• Signal Processing Wireless LAN Processing,
  David Shoemaker, Engim Inc.

6
Three Workshops

• ISSCC Analog Telecom Workshop Backplane
  transceivers, optical and electrical (organizer
  Jan Sevenhans and committee)
• John T. Stonick , Electrical Backplane
  Interconnects to 12Gbps and beyond
• D.V. Plant, Optical Backplanes-Fact or Fiction?
• Kimo Tam, Capacity requirements for high speed
  backplanes
• Muneo Fukaishi, High Data Bandwidth Transceiver
  for Multi-channel Serial Data Communication
• Gerrit den Besten, Opinion about Electrical and
  Optical Backplane Interconnect
• Takeshi Horie, Electrical Interconnect for
  backplanes and short (lt30m) cables
• Michael Neuhaeuser, Transponder and Transceiver
  for serial and parallel optical links with high
  data rates Applications, Design Challenges and
  Trends
• Andy Joy, CMOS Capabillities in Elctrical
  Backplane Transceivers
• ISSCC Microprocessor Workshop Microprocessor
  Design in the Power Constrained Era (organizer
  David Greenhill and digital Sub-committee)
• Sunit Tyagi , Technology review
• Pradip Bose , Architecture for server processors
• Simon Segars , Architecture for mobile processors
• James Warnock, Circuit Design with leaky
  transistors
• TBD, Design with multiple Vdd planes.
• Dave Ayers , Power delivery on the chip
• Larry Smith , Power delivery at the package
  level.
• Ken Goodson , Thermal issues
• SSCTC workshop on "The Implications of CMOS Near
  Its Limits on Circuits and Applications
  (organized by Tak Ning)

7
Short Course

• Design Issues for Systems on a Chip (Organizer
  Terri Fiez)
• Bob Broderson , Technology Scaling Issues
• Ken Kundert , SOC Design and Simulation
• John Fattaruso , Analog Circuit Design
  Considerations
• TBD, RF Design Issues

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Paper Submission Status (as of 8/23)

• Total Papers Submitted 35
• Breakdown by Technical Areas
• Analog 14
• Digital 4
• MEMS, Imagers, Displays 0
• Memory 7
• Signal Processing 2
• Technology Directions 1
• Wireless 3
• Wireline 4
• Breakdown by Region
• US 16
• Far-East 9
• Europe 10
• Total Papers Partially Submitted 138

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Final Paper Submission Stats (11/02)(2002 vs.
2003)