DesignCon 2004

1
DesignCon 2004
Introducing the OIF Common Electrical I/O
Project
2
Agenda

• OIF Overview
• Steve Joiner, Bookham
• CEI Architecture Overview
• Mike Lerer, Xilinx
• CEI Universal Interface
• Pete Hanish,
• Texas Instruments
• CEI 6G LR
• Graeme Boyd, PMC Sierra
• John D Ambrosia,
• Tyco Electronics
• CEI 6G SR and CEI 11G SR
• Tom Palkert, Xilinx

• CEI 11G LR
• Brian Von Herzen, Xilinx
• CEI Testing and Interoperability
• Anthony Sanders,
• Infineon Technologies

3
OIF OverviewSteve Joiner, Bookham

• Launched in April of 1998 with an objective to
  foster development of low-cost and scaleable
  internet using optical technologies
• The only industry group bringing together
  professionals from the data and optical worlds
• Open forum 160 member companies
• international
• carriers
• component and systems vendors
• testing and software companies
• Mission To foster the development and deployment
  of interoperable products and services for data
  switching and routing using optical networking
  technologies

4
OIF Focus

• Low-cost Scaleable Optical Internetworking
• IP-Over-Switched Optical Network Architecture
• Physical layer
• Low-cost optical interfaces between networking
  elements
• Standard device level electrical interfaces for
  low-cost systems
• Control layer interoperability between data and
  optical layers
• Dynamic configuration using IP signaling and
  control mechanisms
• Accommodate legacy network under the new physical
  and control layer mechanisms

5
Output from OIF

• Develop implementation agreements using
• Carrier groups requirements as input
• Physical Layer Users Group requirements as input
  
• Existing standards and specifications when
  available
• Developing new when necessary
• Develop interoperability testing procedure to
  ensure compliance and ultimately interoperable
  products and networks
• Provide input into other standards bodies

6
OIF Directors Officers

• Directors
• Joe Berthold, Ciena
• President
• John McDonough, Cisco
• VicePresident
• Tom Afferton, Northrop Grumman
• Treasurer / Secretary
• Monica Lazer, ATT
• Board Member
• Steve Joiner, Bookham Technologies
• Board Member
• Marco Carugi, Nortel
• Board Member
• Vishnu Shukla, Verizon
• Board Member

• Technical Committee
• Jim Jones, Alcatel
• Chair
• Trey Malpass, Mindspeed
• Vice Chair

• MAE Committee
• Rama Ati, Cisco Systems
• Co-Chair
• Michael Oltmanns,Northrop Grumman
• Co-Chair

7
OIF and Standards Bodies

• Established Liaisons With
• American National Standards Institute - ANSI T1
• International Telecommunications Union - ITU-T
• Internet Engineering Task Force - IETF
• ATM Forum
• IEEE 802.3ae 10 Gb Ethernet
• Network Processing Forum - NPF
• Metro Ethernet Forum MEF
• Rapid I/O
• Tele Management Forum TMF
• XFP MSA Group

8
Technical Committee Six Working Groups

• Architecture Signaling
• Services, network requirements and architectures
• Protocols for automatic setup of lightpaths
• Carrier
• Requirements and applications
• OAMP (Operations, Administration, Maintenance
  and Provisioning)
• Network management
• Interoperability
• Interoperability testing
• Physical and Link Layer
• Equipment and subsystem module interfaces
• Physical Layer User
• Requirements and applications

9
Development of OIF Implementation Agreements
Define and Start Project
Principal Member Ballot Comments and IPR call
Develop Draft IA (contribution driven process)
Straw Ballot Comments and IPR call
Passes gt75 ?
No
Passes gt50? Resolve Comments
Yes
Implementation Agreement
Major Technical changes ?
Yes
No
10
CEI Overview Mike Lerer, Xilinx

• CEI Project Problem Statement
• A faster electrical interface is required to
  provide higher density and/or lower cost
  interfaces for payloads of 10Gbps and higher
• Including
• SERDES to Framer Interface (SFI)
• System Packet Interface (SPI)
• TDM-Fabric to Framer Interface (TFI)

11
PLL Interfaces

• SFI SerDes Framer
• SPI System Packet, TFI TDM Fabric

SERDES Framer Interface (SFI)
Optical Interface
SERDES Framer Interface (SFI)
System Packet Interface (SPI)
SERDES Device and Optics
PHY Device
FEC
OR
TDM Fabric to Framer Interface (TFI)
12
CEI Protocol (CEI P)

• CEI Protocol Project Problem Statement
• To define protocols that take advantage of the
  faster electrical interface developed by the CEI
  project. The target is to provide higher density
  and/or lower cost interfaces for payloads of
  10Gbps and higher, including SERDES to Framer
  Interface (SFI), System Packet Interface (SPI),
  TDM-Fabric to Framer Interface (TFI), 8b/10b
  based Interfaces.
• Objectives
• Shall conform to the data characteristics
  required by the CEI project (Eg., DC balance,
  Transition density, Max run-length)
• Support a wide range of client signals including
  SFI, SPI, TFI, 8b/10b Interfaces

13
CEI Project Scope (1 of 2)

• Electrical and jitter specifications for future
  interfaces including SFI, SPI and TFI.
• The project shall define
• CEI-6G-SR A 6 Gigabit short reach link
• 0 to 200mm link with up to one connector
• Data lane(s) that support bit rates from 4.976 to
  6Gbps over Printed Circuit Boards.
• CEI-6G-LR A 6G long reach link
• 0 to 1m link with up to two connectors
• Data lane(s) that support bit rates from 4.976 to
  6Gbps over Printed Circuit Boards.
• CEI-11G-SR An 11G short reach link
• 0 to 200mm link with up to one connector
• Data lane(s) that support bit rates from 9.95 to
  11Gbps over Printed Circuit Boards.
• CEI-11G-LR An 11G long reach link
• 0 to 1m link with up to two connectors
• Data lane(s) that support bit rates from 9.95 to
  11Gbps over Printed Circuit Boards.

14
CEI Project Scope (2 of 2)

• The Implementation Agreement shall define the
  applicable data characteristics
• e.g. DC balance, transition density, maximum run
  length
• The Implementation Agreement shall define channel
  models and compliance points / parameters.
• The Implementation Agreement shall not
• Define the pin assignments or select a specific
  connector
• Define a management interface

15
CEI Project Objectives Requirements(1 of 2)

• The Implementation Agreement(s) shall allow
  single and multi-lane applications
• Shall support AC coupling
• Shall support hot plug
• Shall achieve Bit Error Ratio of better than
  10-15 per lane with the test requirement of 10-12
  per lane

16
CEI Project Objectives Requirements(2 of 2)

• Short and long reach links should interoperate
  under 200mm
• Shall define an 11G short reach link that is
  capable of supporting SONET/SDH compliance at the
  optical carrier (OC) interface.
• The 6G long reach link shall accommodate legacy
  IEEE 802.3 XAUI and TFI-5 compliant backplanes.
• The primary focus of the CEI-11G-LR
  implementation agreement will be for non-legacy
  applications, optimized for overall
  cost-effective system performance including total
  power dissipation

17
CEI Project Deliverables

• An Implementation Agreement with clauses which
  shall cover
• Interoperability, Jitter Compliance Methodology
• CEI-6G-SR 6G Short Reach
• for 0 to 200mm and up to 1 connector
• CEI-6G-LR 6G Long Reach
• for 0 to 1m and up to 2 connectors
• CEI-11G-SR 11G Short Reach
• for 0 to 200mm and up to 1 connector
• CEI-11G-LR 11G Long Reach
• for 0 to 1m and up to 2 connectors

18
CEI Project Schedule

• CEI
• Includes
• Interoperability, Jitter Compliance Methodology
• CEI-6G-SR
• CEI-6G-LR
• CEI-11G-SR
• Now going to fourth round of straw ballot cycles
• Additional Clause 9
• Adds
• CEI-11G-LR
• Now going to second round of straw ballot cycles
• Remember
• Straw Ballots continue until there are no
  additional technical changes.
• Followed by Principal Member Ballot with no
  technical changes and the specification is
  published.

19
CEI Universal Electrical Interface Optimized for
System Design Pete Hanish, Texas Instruments

• Minimize overall throughput cost for higher
  capacity systems
• Groundwork for 6G/11G PHY interfaces
• Deliver value to the entire system chain
• Decrease overall system cost
• Interoperable components for system vendor
  options
• Development cost leverage for component vendors
• Fosters interoperability
• Verification method to ensure interoperability
• Demonstrations already taking place

20
CEI Universal Electrical Interface Optimized for
System Design

• Broad application space
• Standard products, system-on-a-chip, FPGAs,
  ASICs
• Multiple technology nodes
• Interface specifies only electrical and jitter
• Building block for protocols likeCEI-P, TFI-x,
  SFI-x, SPI-x, other interfaces
• Backplanes, networking, interconnect, CPU
  interface
• Opportunity to converge standards
• Higher layer standardization flexible
• Liaisons with several bodies

21
CEI Universal Electrical Interface Flexibility
0 200mm or 0 1000mm
4.976 6.375Gbps or 9.95 11.1Gbps

• Does specify
• Data char Channel models
• Compliance points Jitter
• BER

• Does not specify
• Lane count Pinout
• Mgt interface Power supply
• Connector High level fn

22
CEI Universal Electrical Interface Feasibility
Demonstration 2003

• SuperComm 2003
• CEI-6G-LR
• Validated transceivers and connectors
• CEI-11G-SR
• Validated round robin interoperability of SERDES
  devices, connectors and optical transceivers
• CEI-11G-LR
• Multiple backplane and signaling demonstrations

23
CEI Universal Electrical Interface
10GBE 10GBFC OC-192 OC-768
CEI-11G-SR
CEI-11G-SR
CEI-6G-LR
24
CEI Universal Electrical Interface 11G-LR
Industry Development
CEI-11G-SR
CEI-11G-SR
CEI-11G-LR
25
Interoperability Strategy Anthony Sanders,
Infineon Technologies

• Define exact compliancy tests for transmitter in
  terms of eye masks, output jitter and ability to
  perform emphasis
• Define compliancy test for channels using worst
  case transmitter and reference receiver
• Give guidelines concerning channel construction
  and frequency domain performance
• Receiver must be able to tolerate any combination
  of compliant transmitter and compliant channel
  thus not restricting the market in terms of
  developed solutions.

26
Channel Interoperability Strategy

• Backplanes are measured using traditional network
  analysers and cascaded with a worse case model

• of the transmitter and receiver return loss
• The receiver pulse response is then calculated
  for a given transmitter pulse shape

27
Channel Compliance using StatEye

• New methodology in the analysis of channel
  equalisation is developed which allows the exact

statistical nature of the frequency response,
crosstalk and jitter to be analysis in terms of a
effective receiver eye.
28
CEI-6G OverviewGraeme Boyd, PMC Sierra

• Definition
• Requirements
• Channel information
• Some typical applications
• Restrictions
• Specifications
• Verification that specifications meet requirements

29
CEI-6G Definition

• Electrical and jitter specifications for future
  interfaces including SFI, SPI and TFI for OIF as
  well as for other interfaces unrelated to OIF
  (examples could include Serial Rapid IO, SAS,
  Ethernet). It does not contain any protocol
  implementations (that is contained within the
  OIFs CEI-P document or within other standards).
• A CEI-6G Short Reach specification for Data
  lane(s) that support bit rates from 4.976 to
  6Gsym/s over Printed Circuit Boards.
• Physical reach between 0 to 200mm and up to 1
  connector.
• A CEI-6G Long Reach specification for Data
  lane(s) that support bit rates from 4.976 to
  6Gsym/s over Printed Circuit Boards.
• Physical reach between 0 to 1m and up to 2
  connectors.

30
CEI-6G Requirements

• Support serial baud rate from 4.976Gsym/s to
  6.375Gsym/s.
• Capable of low bit error rate (required BER of
  10-15 with a test requirement to verify to
  10-12).
• Short Reach
• Capable of driving 0 - 200mm of PCB and up to 1
  connector.
• Long Reach
• Capable of driving 0 - 1m of PCB (such as IEEE
  802.3 XAUI or TFI-5 compliant backplane) and up
  to 2 connector for long reach
• Shall support AC coupled operation and optionally
  DC coupled operation
• Shall allow single or multi-lanes.
• Shall support hot plug.

31
HM-Zd XAUI Backplane Layer Variation _at_ 20 Inches
32
HM-Zd Legacy Backplane 36 Length
Configuration Variation
Very different channel return loss
Reflections moved significantly
33
HM-Zd Legacy Backplane 36 Length
Configuration Variation
Large group delay differences for return loss
34
HM-Zd Legacy Backplane 36 Length
Configuration Variation
Modeling chip RL as RC to the 8dB spec
Perfect chip RL
35
HM-Zd Legacy Backplane 36 Length
Configuration Variation
Fails channel compliance
Passes channel compliance
Large differences in the resulting eye after
ideal DFE depending on length on line cards and
the backplane
36
CEI-6G Some typical applications

• Multiplexing a 16-lane SFI-5 or SPI-5 link to a
  8-lane CEI-6G short reach link
• Multiplexing a 16-lane SFI-5 or SPI-5 link to a
  8-lane CEI-6G long reach link, thus allowing the
  signals across a backplane
• Multiplexing 2n TFI-5 links to a n-lane CEI-6G
  long reach links
• Multiplexing a 4-lane XAUI or 10G Fiber Channel
  link to a 2-lane CEI-6G LR link
• Doubling the speed of a 16-lane SPI-5 link to a
  16-lane CEI-6G link, thus allowing up to a
  factor of 2 over-speed for packet processors
• Custom higher speed interconnect and/or backplanes

37
CEI-6G Restrictions

• Average transition density and average DC balance
  needs to converge to 0.5 over a long period (gt109
  bits) with a probability of at least one minus
  the BER ratio.
• Probability of run lengths over 10 to be
  proportional to 2-N for N-like bits in a row
  (N?10). Hence, a run length of 40 bits would
  occur with a max probability of 2-40.
• If a fixed block coding scheme is used (e.g.
  8B/10B), the input data must be either be
  scrambled before coding or the coded data must be
  scrambled prior to transmission.
• This will prevent input data creating killer
  patterns (e.g. CJPAT patterns).

38
CEI-6G Restrictions

• The ground difference between the driver and the
  receiver shall be within 50mV for SR links and
  100mV for LR links.
• Both driver and receiver lane-to-lane skew are
  each allowed up to 500ps. Higher layers must
  allow for this (1ns) skew as well as some PCB
  skew.
• Rather than specifying materials, channel
  components, or configurations, the IA focuses on
  effective channel characteristics.
• Hence a short length of poorer material should be
  equivalent to a longer length of premium
  material. A length is effectively defined in
  terms of its attenuation rather than its physical
  length.

39
CEI-6G Restrictions

• So for CEI-6G-SR we have the standard open eye at
  the receiver, however for CEI-6G-LR the eye is
  closed at the receiver hence requiring receiver
  equalization.

40
CEI-6G Main Transmitter Specifications
41
CEI-6G Main Receiver Specifications
42
CEI-6G Verification

• A large amount of work is ongoing in the Jitter
  and Interoperability area given the BER
  requirements to insure different vendors chips
  can talk with each other.
• For CEI-6G-SR the OIF has chosen to specify the
  transmitter and receiver. This then implies what
  are compliment channels.
• Similar to most other SERDES standards, except
  that OIF is using statistical eyes rather than
  worst case eyes.
• As CEI-6G-LR can have a closed eye at the
  receiver, standard methods do not work anymore,
  so OIF has chosen to move the receiver spec
  point to after an ideal 5 tap DFE. Thus
  specifying the transmitter and compliment
  channels while implying the receiver spec.
• So however the real receiver is implemented it
  needs to be equivalent or better than a 5 tap DFE.

43
OIF Electrical Specifications Tom Palkert, Xilinx

• SFI SERDES to Framer Interface
• SPI System Packet Interface
• TFI TDM Fabric Interface
• SxI 2.5 Gbps Electrical Specification
• CEI 6G and 11G Electrical Specification

44
CEI-11G Short Reach Requirements
1. Support serial data rate from 9.95 to 11. 1
Gsym/s.
2. Capable of low bit error rate (required BER of
10-15 )
3. Capable of driving 0 to 200 mm of PCB and up
to 1 connector.
4. Shall support AC-coupled and optionally
DC-coupled operation.
5. Shall allow multi-lanes (1 to n).
6. Shall support hot plug.
45
OIF Electrical Specifications
OR
46
CEI Short Reach Common Electrical Interface
SERDES Framer Interface (SFI)
Optical Interface
System Packet Interface (SPI)
CEI-11G-SR
CEI-11G-SR
CEI-11G-SR
SERDES Device and Optics
PHY Device
Data
Data
47
CEI Common Electrical Interface
SERDES Framer Interface (SFI)
SERDES Framer Interface (SFI-5)
System Packet Interface (SPI-5)
Transmit Interface (SPI-5)
FEC Device
PHY Device
Transmit Link Layer Device
Data
Data
Data
Status
Receive Link Layer Device
Data
Data
Data
Status
Receive Interface (SPI-5)
Provide well defined voltage levels and jitter
budgets
48
Common Electrical Interface Short Reach
SERDES Framer Interface (SFI)
System Packet Interface (SPI)
SERDES Framer Interface (SFI)
Optical Interface
Transmit Interface (SPI-5)
SERDES Device And Optics
FEC Device
PHY Device
Transmit Link Layer Device
Data
Data
Data
Status
8"
8"
8"
Receive Link Layer Device
Data
Data
Data
Status
Receive Interface (SPI-5)
Capable of driving at least 8 inches of FR4 with
1 connector
49
OIF-SFI-4 phase 1
S y s t e m t o O p t i c s
SERDES Device And Optics
Framer
FEC Processor
O p t i c s t o S y s t e m
50
Possible OIF-SFI-4 phase 3
S y s t e m t o O p t i c s
SERDES Device And Optics
Framer
FEC Processor
O p t i c s t o S y s t e m
51
CEI-11G-SR Common Electrical Interface
Serdes
FEC Processor
TXDATA
Differential signal amplitude V
Normalized bit time UI
RXDATA
The receive eye mask specifies the jitter at the
end of the line
52
CEI-11G-SR Common Electrical Interface
Serdes
FEC Processor
TXDATA
Differential signal amplitude V
Normalized bit time UI
RXDATA
The transmit eye mask specifies the jitter at the
beginning of the line
53
CEI-11G-SR RX eye diagram
525 mv
R_Y2
55 mv
R_Y1
Normalized amplitude
0
-R_Y1
-R_Y2
0.0
R_X1
1.0
1-R_X1
0.5
.35UI
Normalized bit time UI
Receiver input mask
54
CEI-11G-SR TX eye diagram
385 mv
T_Y2
T_Y1
180 mv
Normalized amplitude
0
-T_Y1
-T_Y2
0.0
T_X1
1.0
1-T_X2
T_X2
1-T_X1
.15UI
Normalized bit time UI
Transmit eye mask
.40UI
55
Jitter Egress Receiver Input Telecom Sinusoidal
Jitter
15.2
-20dB/Dec
1.7
Sinusoidal Jitter Tolerance (UIp-p)
0.17
0.05
0.01E-3
2E-3
80
0.12
17.9E-3
4.08
Frequency (MHz)
56
Jitter Ingress Receiver Input Telecom Sinusoidal
Jitter
17
-20dB/Dec
1.7
Sinusoidal Jitter Tolerance (UIp-p)
0.17
0.05
0.01E-3
2E-3
80
0.4
20E-3
4
8
27.2
Frequency (MHz)
57
CEI-11G-LR RequirementsBrian Von Herzen,
Xilinx

• Support baud rate from 9.95 Gig/sec to 11.1
  Gig/sec
• Long Reach
• Capable of driving 0 - 1m (39 inches) of PCB
• up to 2 connectors
• Optimized for Non-Legacy Systems (Greenfield)
• Optimize System cost including Power Dissipation
• Capable of low bit error rate (required BER of
  10-15 or better)
• Shall support AC coupled operation, DC Coupling
  Optional.
• Shall allow multi-lanes (1 to n).
• Shall support hot plug.
• Shall interoperate with CEI-11G-SR up to 200mm (8
  inches).

58
CEI-11G-LR Backplane Applications
59
CEI-11G-LR Connections up to 1 meter
60
CEI-11G-LR Issues

• Losses
• Chip Packaging
• Insertion loss, reflections and impedance
  mismatches
• Backplane Connectors
• Vias
• Cu Losses skin effect, AC impedance, bulk R
• Dielectric losses
• Impedance Discontinuities
• Reflections
• Noise
• Crosstalk

61
CEI-11G-LR General Characteristics

• High-Speed Low Voltage Differential Drive
• Unidirectional Point to Point Signaling
• Uses Balanced Differential Pairs
• Uses Differential 100-Ohm Nominal Impedance
• Signal Scrambled Non Return to Zero (NRZ)

62
CEI-11G-LR Specification Approach

• Transmitter Specified
• Tx Eye Diagram
• Channel Compliance
• Channel Specified with S Parameters
• Compliance determined with Simulation Script
• A compliant receiver shall operate with any
  compliant Tx and compliant channel
• If Tx and Channel are compliant, receiver must
  work.

63
CEI-11G-LR Solutions

• NRZ Signaling
• The Transmitter
• Tx Equalization
• Pre-emphasis of High Frequency
• Compensates for Channel Loss
• The Channel
• PCB Materials
• Connectors
• IC Packaging
• Manufacturing / Layout Techniques
• Assumes Closed Eye at Receiver
• The Receiver
• Rx Equalization
• Opens Eye
• Compensates for High Frequency Losses
• Compensates for Impedance Discontinuity
• Compensates for Reflections

Note Solution space may grow with continued
development and further input from industry on
application needs.
64
CEI-11G-LR Summary

• CEI-11G Long Reach provides a robust solution
• 9.953 to 11 Gbps
• NRZ solution
• Up to 1 meter propagation distance
• 10-15 base error rate, correctable to 10-20 or
  better
• Suitable for next-generation 10G system
  backplane requirements

65
Transmitter Eye Mask Anthony Sanders, Infineon
Technologies

• Eye Mask defines limits of the transmit jitter
  and amplitude but must be measured using a Golden
  PLL
• Given finite sampling of signal, peak value of
  time jitter must be adjusted

66
Measuring Output Jitter

• Output Jitter is traditionally measured using a
  Bit Error Tester that is capable of introducing a
  variable time delay into the trigger path.
• A plot of the measured BER against time delay is
  commonly known as a Bathtub measurement

67
Jitter Terminology

• Unbounded Gaussian Jitter a.k.a. Random Jitter
• Uncorrelated Bounded High Probability Jitter
  a.k.a. Deterministic Jitter
• Correlated Bounded Gaussian Jitter, caused by
  Amplitude to Time conversion of ISI, becomes
  Correlated Bounded High Probability Jitter at
  some Error Rate

68
Jitter Tolerance Testing

• For short reach, Jitter tolerance is performed
  using a stressed eye with a defined amount of
  jitter and a signal eye just at the limited of
  the defined received eye mask

69
Jitter Tolerance Testing

• For long reach the inclusion of a compliant
  channel is used to generate a known amount of ISI

70
CEI Protocol Project Builds on CEI to Define
these Interfaces
10GBE 10GBFC OC-192 OC-768
CEI-11G-SR
CEI-11G-SR
CEI-6G-LR
71
It is the mission of the OIF to support the
industry by sharing the results of its efforts
with other organizations.
72
Thank You!