1CADENCE DESIGN SYSTEMS, INC'

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SCE-MI 2.0, Cadence Summary(Accellera ITC
Meeting)

• Feb 17, 2005

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SCE-MI CPD Meets ITC Stated Goals

• Support for Variable-Length Messages (VLMs)
• Eases task of writing BFMs
• Enables SCE-MI infrastructure to optimize
  transport of VLMs
• Eliminate Uncontrolled Clock
• Eases task of writing BFMs
• Backward Compatibility
• Maintain SCE-MI 1.0 functionality, 1.0 2.0 BFMs
  can coexist
• Maintain focus on performance

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Native VLM Support Simplifies BFM

• VLM macro eliminates clock control
• Interaction of multiple message ports compounds
  problem in 1.0

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Native VLMs Enable Higher Performance

• SCE-MI Infrastructure can optimize VLM transport
• Multiple message words transferred across HW/SW
  interface in one operation
• Hardware-Side (Emulator) handles message
  segmentation for input ports, aggregation for
  output ports

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SCE-MI 2.0 Desirable Characteristics

• Language Neutrality
• C/C
• Synthesizable Verilog/VHDL/SystemVerilog
• Platform Neutrality
• Simulation/Acceleration, Event-Based/Cycle-Based
• Support Ease-of-Use/Performance trade-off
• SCE-MI 1.0/2.0 compatibility and co-existence
  allows selection of appropriate mechanism

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Language Neutrality

• SCE-MI CPD maintains SCE-MI language neutrality

TLM
RTL
C/C
TLM
C/C
TLM
SW Side
HW Side

• Abstract proxies easily created for SW-side (e.g.
  TLM)
• Standard RTL on HW-side supported by a broad
  range of vendors and applications

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Platform Neutrality

• Use of CPD macros eliminate the need for clock
  control
• Unbounded Zero-Time Operations do not exist

Sim Kernel
wait()
schedService()
serviceLoop()
SW Side
HW Side

• SW side and HW side run in a single-process
  simulation

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1.0/CPD Compatibility

• CPD macro semantics can be defined in terms of
  1.0 macros
• Ease support for SCE-MI 1.0 vendors
• Ensure compatibility of 1.0/CPD semantics

ClockNumN
Cclock
Clock
ClockNumN
TransmitReady
TransmitReady
SceMiClockPort
ReceiveReady
ReadyForCclock
TransmitLast
Message
Message
w
w1
SceMiMessageOutPort
SceMiClockControl
SceMiVarMessageOutPort
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Streaming for Performance
Deferred isReady
SW Side
3
HW Side
isReady

• Steaming allows longer free-run times in emulator
• Slightly modified isReady semantics enable
  streaming
• Applicable to non-reactive tests

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SCE-MI CPD Incremental Improvement
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SCE-MI CPD Exceeds ITC Stated Goals

• Support for Variable-Length Messages (VLMs)
• Eliminate Uncontrolled Clock
• Backward Compatibility
• Platform Neutrality
• Streaming Capable for Performance

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