CSE 573S: Networking Protocols

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CSE 573S Networking Protocols
Switching Systems
Instructor Manfred Georg Guest Speaker Charlie
Wiseman
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Switching in Modern Communication Networks
Slides taken from various lecture notes by Dr.
Jonathan Turner
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Switching Systems

• Cell Based Switches
• IP Lookup (using Tries)?
• ATM Cell Structure
• IP over ATM
• Switch Architectures
• Buffered Multistage Switches
• Resequencing
• Multistage Switch Topologies
• Multistage Switches with Static Routing
• Clos Network
• Sorting Networks

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Benes Network - Structure and Routing
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
1010 1011 1100 1101 1110 1111

• Network expanded by adding stages on left and
  right.
• 2k?1 stage network with d port switch elements
  supports up to dk ports
• network topology called the Benes network
• First k???stages of ?k???stage network do traffic
  distribution.
• Load distribution guarantees internal load
  ??external load.
• For d-ary switches, route on base d digits of
  output address.

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Overload in Extended Delta Networks

• First h stages distribute traffic, last k route.
• When h k ??1, ext. delta network is same as
  Benes network
• Network cannot be overloaded if S ??d ?(k?h)/???
  where S is speedup?
• Result holds for both unicast and multicast.
• When h k ??1, no speedup needed.

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Switching Systems

• Cell Based Switches
• IP Lookup (using Tries)?
• ATM Cell Structure
• IP over ATM
• Switch Architectures
• Buffered Multistage Switches
• Resequencing
• Multistage Switch Topologies
• Multistage Switches with Static Routing
• Clos Network
• Sorting Networks

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Resequencing
Input Line Cards
Output Line Cards
Load Balancing Stage
Shared Memory Switch Elements

• Multistage interconnection networks with buffered
  switch elements and dynamic routing.
• scalable, bandwidth-efficient architecture
• single chip can provide 100 Gb/s throughput and
  buffer thousands of cells

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Resequencing with Sequence Numbers
Sequence Numbers Added
Reseq. Arrays indexed by seq.

• Drawbacks
• each output needs N resequencing arrays
• initialization when line card comes on-line
• timeouts needed to cope with lost cells
• multicast requires per flow resequencing arrays

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Time-Based Resequencing
Timestamp Ordered Reseq. Buffer
Timestamps Added
Output Buffer

• Single resequencing buffer per output.
• Cells held until age exceeds threshold (T ).
• Options for late cells.
• discard (strict resequencing) or buffer (loose)?

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Henrions Strict Resequencer Design
T slot timing wheel
current time modulo T
insert at timestamp mod T
ready cells

• Implemented using linked lists in common memory.
• Constant time per cell.

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Performance of Strict Resequencing

• Simple random traffic.
• 3 stage network, 8 port SEs, 512 (shared) cell
  buffers.
• 1st stage SEs use round robin load balancing for
  each input.

Late cells rare with small speedup
For systems with 10G links, delay for 256 cells
is 10 ?s.
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Performance on Adversarial Traffic
21 overload at target output
Delay drops as SE buffers drain
Resequencer recovers when delay drops below T
Growing network delay
Cells discarded when delay exceeds T
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Switching Systems

• Cell Based Switches
• IP Lookup (using Tries)?
• ATM Cell Structure
• IP over ATM
• Switch Architectures
• Buffered Multistage Switches
• Resequencing
• Multistage Switch Topologies
• Multistage Switches with Static Routing
• Clos Network
• Sorting Networks

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Routing in Delta Networks

• Route from any input x to output y by selecting
  links determined by successive d-ary digits of
  ys label.
• This process is reversible we can route from
  output y back to x by following the links
  determined by successive digits of xs label.
• This property (often called the self-routing
  property) allows for simple hardware-based
  routing of cells.
• Note that the forward self-routing property holds
  even if the links connecting to a given
  subnetwork are rearranged.

0101
0
1
1
0
1
1
0
1101
1
xxk-1 . . . x0
yyk-1 . . . y0
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Isomorphisms Between Networks

• Two networks are the isomorphic if they are
  structurally identical that is, if you can map
  one network to the other by renumbering inputs,
  outputs and switches.
• Two networks are strongly isomorphic if one can
  be mapped to the other by just renumbering the
  switches. Strong isomorphism is denoted by ?.
• If N1?????then in any network that contains N1,
  we can substitute ??, without changing the
  overall structure.

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Omega Network

• For klogdn the omega network ?n,d is defined by
  ?n,d?kn,d , where

• The omega network is isomorpic (but not strongly
  isomorphic) to the delta network.
• Successor function is ?(i,j)?-1d(j,k).
• The uniform interconnection pattern can be useful.

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Illustration of Isomorphisms
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Switching Systems

• Cell Based Switches
• IP Lookup (using Tries)?
• ATM Cell Structure
• IP over ATM
• Switch Architectures
• Buffered Multistage Switches
• Resequencing
• Multistage Switch Topologies
• Multistage Switches with Static Routing
• Clos Network
• Sorting Networks

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Multistage Networks with Static Routing

• All cells in a session follow a specific
  pre-assigned path.
• Requires path hunt and resource reservation.
• creates potential for blocking
• Eliminates need for resequencing and distributed
  scheduling.

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General Design Issues

• Path hunting
• how to rapidly find path with sufficient capacity
• Blocking
• session requests block if no path available with
  sufficient bandwidth
• can configure systems to be nonblocking
• alternatively, can accept some small blocking
  probability

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Naive Non-Blocking Network

• Connect Inputs and Outputs using a grid
  (Crossbar)?
• Can we do better?

Crosspoint Count N2
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Switching Systems

• Cell Based Switches
• IP Lookup (using Tries)?
• ATM Cell Structure
• IP over ATM
• Switch Architectures
• Buffered Multistage Switches
• Resequencing
• Multistage Switch Topologies
• Multistage Switches with Static Routing
• Clos Network
• Sorting Networks

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The Clos Network

• Let d, r, n be integers where d divides n evenly.
  The three stage Clos network is defined by

• C 3n,d,r is strictly nonblocking for unicast
  sessions if and only if r ??d1.

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Complexity of Clos Network

• The crosspoint count for a three stage Clos
  network is 2dr(n?d)r(n?d)2.
• if we substitute r2d, making the network
  nonblocking, this becomes 2n(2dn/d)?
• the crosspoint count is minimized by taking
  d(n?2)1/2
• this gives a crosspoint count of 4?21/2n 3/2
  ?????n 3/2?
• Another nonblocking network can be obtained by
  replacing the middle stage switches by Clos
  networks.

• C5 is also nonblocking when r ?2d?1. If r2d and
  d(2n/3)1/3, the crosspoint count is ?????n ????
• this generalizes to C 2k?1, which is nonblocking
  when r?2d ?1. If r2d and d(2k-1(k
  ?1)n/4(2k-1?1))1/k, the crosspoint count is

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Switching Systems

• Cell Based Switches
• IP Lookup (using Tries)?
• ATM Cell Structure
• IP over ATM
• Switch Architectures
• Buffered Multistage Switches
• Resequencing
• Multistage Switch Topologies
• Multistage Switches with Static Routing
• Clos Network
• Sorting Networks

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Sorting Networks

• Bitonic sorter recursively merges sorted
  sublists.
• Can switch by sorting on destination.
• additional components needed for conflict
  resolution

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Design of Sorting Network

• In bit-serial sorting element, sorting keys are
  compared bit by bit as header is received.
• Comparison starts with MSB, so first difference
  determines larger key.
• Upstream acknowledgement path used in some
  systems.
• Single bit delay, simple circuit (about 50 gates)?