MultiVDD FPGA Architecture

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Multi-VDD FPGA Architecture

• CSE 598C Project
• Fall 2003
• Aman Gayasen, Ki-Yong Lee

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FPGA overview Virtex-II architecture
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Power Consumption in FPGAs

• Orders of magnitude larger than embedded
  processors (that are being used in mobile devices
  extensively)
• No embedded FPGA yet (but on its way)
• Static (leakage) power
• Smallest Virtex-II 200 mW
• No standby modes

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Dynamic Power Breakdownin Virtex-II
Taken from Li Shang et al. FPGA02
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Leakage Power Breakdownof a 90 nm CLB array
(Spartan 3)
Leakage in Configuration SRAMs can be easily
optimized, using conventional techniques

• Leakage in Virtex-II FPGA
• 25 of total power (average)
• 200 mW for smaller Virtex-II devices (0.13 nm)
• 540 mW for largest Virtex-II devices

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Leakage Recap -Dependence on Vdd

• Sub-threshold leakage a Vdd
• DIBL a exp(Vdd)
• Gate Leakage a exp(Vdd)

Lowering Vdd is a good idea to reduce leakage
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Multi-Vdd Strategy

• Let the non-critical paths run at lower voltage
• Saves dynamic static power
• Can maintain performance while saving power

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Issues in multi-Vdd Approach

• Optimal voltage assignment is an NP- complete
  problem.
• Level Converters need to be inserted if a low-Vdd
  gate drives a high-Vdd gate
• Consume power. Introduce delay.

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Multi-Vdd FPGA

• Expected to reduce dynamic static power
  consumption of logic as well as routing
  resources.
• May need redundant level converters because
  different designs may need different
  number/placement of level converters.

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Versatile Place and Route (VPR) -An FPGA Place
and Route tool

• Developed at Univ. Toronto
• Open source.
• Flexible.
• Can specify various architectural parameters as
  inputs
• Simple architecture.
• Basic CLB design similar to Xilinx/Altera FPGAs

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VPR Example architectural parameters

• LUT size/inputs
• Number of slices (subblocks) in a CLB
• Various parameters associated with routing
  matrix.
• Delay values for Timing-Driven Routing

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Algorithm for assigning Vdds(for 2 Vdds)

• List out the paths whose delays become greater
  than required clock time period when they are
  operated at low Vdd.
• Assign a criticality attribute to each node. This
  is a measure of how many paths contain this node.
• Mark all nodes on critical path as high Vdd.
• For every other path, traverse the nodes in
  decreasing order of criticality, and mark them as
  high Vdd till the path delay Tclock

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Algorithm for finding k longest paths from a
timing graph

• Generate the longest path P1
• Prepare list1 ordered list of branch slacks
• Calculate next_delay(P1)
• While (k paths not enough)
• I the path with longest next_delay
• J first branch point in list1
• Generate next longest path Pk1 by branching
  out from the j-th node on path Pi
• Prepare listk1 and calculate next_delay(Pk1)
• Update next_delay(Pi)
• K k 1

Source Ju et al. DAC 1991
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Results

• Assuming a 20 increase in delay of circuit when
  it operates at low Vdd, it is observed that gt 60
  of the nodes can be made low Vdd without
  increasing the Tclock.
• (This does not mean that 60 of the circuit can
  run at low Vdd. A node in the timing graph does
  not always result in an independent circuit
  element.)

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Circuit Level Work

• 1. Logic Slice
• 2. D-flipflop
• 3. Level Converter

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Logic Slice Design

• 65nm, BSIM4 model
• K-input LUT Transmission gate mux
• Edge-Triggered D-Flipflop

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Logic Slice

• Combinational Logic Delay T_comb (psec)

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Logic Slice

• Sequential Logic Delay T_seq_in (psec)

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Logic Slice

• Sequential Logic Delay T_seq_out (psec)

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Logic Slice

• Dynamic Power (uW)
• Freq500MHz

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Logic Slice

• Leakage Current (uA)

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D-Flipflop

• Dynamic Power (uW) at Freq500MHz
• Compared with 0.18um technology

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D-Flipflop Comparison

• Leakage Current

I (pA)
I (nA)
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Level Converter

• Design
• 65nm, BSIM4 model
• Delay, Dynamic Power, Leakage Current

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Level Converter

• Delay (psec)

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Level Converter

• Dynamic Power (uW)
• Freq500MHz

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Level Converter

• Leakage Current (nA)

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Summary