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Signal Processing for Storage

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Title: Signal Processing for Storage


1
Signal Processing for Storage
  • Borivoje Nikolic
  • Department of Electrical Engineering and Computer
    Sciences
  • University of California at Berkeley
  • bora_at_eecs.berkeley.edu

2
Marvel of Technology
3
Disk Drives
  • 1956 IBM engineers in San Jose introduced the
    first computer disk storage system
  • The 305 RAMAC (Random Access Method of Accounting
    and Control) could store five million characters
    (five megabytes) of data on 50 disks, each 24
    inches in diameter.

4
Todays Disks
  • IBM Travelstar 17.1 Gb/in2
  • Experimental densities 35-Gb/in2 every square
    inch of disk space could hold 4.37 GB -- nearly
    as much data as a 5.25-inch diameter DVD-ROM.
    (4.7 GB per surface) or seven CD-ROMs (each 650
    MB).
  • NSIC is about to demonstrate 100Gb/in2
  • Desktop/platter (3.5-inch diameter) 50 GB
  • Notebook/platter (2.5-inch) gt20 GB
  • Microdrive (1-inch) gt 2 GB.

5
Trends in Magnetic Disk Drives
  • Exponential growth in capacity is due to
  • reduction of head flying height
  • reduction of the gap size in the head
  • reduction of the media thickness
  • advanced signal processing methods
  • advanced digitalintegrated circuits

Areal density of data in disk drives
6
IBMs Areal Densities
http//www.storage.ibm.com/technolo/grochows/groch
o01.htm
7
Datarate Trends in Disk Drives
Source ISSCC
8
Flight Height
Rotation speeds 4500 15000 rpm
9
Price Trends
10
Magnetic Recording Fundamentals
Magnetic Disk Track Recording
Magnetization Levels
Detected signal in the Head
11
Magnetic Recording Fundamentals
  • Increased recording density results in
  • reduced peak amplitude
  • peak shift

Reduced Amplitude
Isolated Pulses
Superposed Pulses
Peak Shift
12
Lorentzian Pulse
Lorentzian
13
Bandlimited Channels
Spectral control (ISI
control) SNR limitation
Towards Shannon capacity

Equalization - Partial response
Channel coding - Trellis/Parity coding
Combined coding and Equalization - Iterative
coding
Going to 1Tb/in2 density will lower the SNR by
another 6dB
14
Signal Equalization
  • Lorenzian Pulse
  • Equalization (1-D)(1D)n

1.0
0.5
PW50
User density PW50/T
(1-D)(1D)
(1-D)(1D)2
(1-D)(1D)3
2
3
1
1
1
EPR4
E2PR4
PR4
15
Signal Response
  • Simulated readback signal User density 1.4
    User density 3.0

16
Read Channel Building Blocks
WriteSignal
WriteData
Encoder
Scrambler
Precomp
Servo
ReadSignal
VGA
CT Filter
Equalizer
Detector
ADC
ReadData
Decoder
Descrambler
Timing recovery
17
Amplitude Spectra
18
Equalization Targets
19
Eye Diagrams
PR4
EPR4
20
Maximum Likelihood Detection
21
The Viterbi Detector
  • Equalization Response Memory StatesPR4 1-D
    2 2 4 (2)EPR4
    (1-D)(1D)2 3 8E2PR4 (1-D)(1D)3
    4 16
  • Alternative is to use DFEnot used in practice
    because of error propagation

22
Error Distances
  • Channel input error sequence
  • Channel output error sequence
  • Squared Euclidean error distance

23
Error Probability
  • Probability of misdetection of sequence Sk by Sk
    is a function of error distance, dK
  • Performance of the PRML system is determined by
    the minimum distance error events

Error event distance spectrum
Q () - Error function
24
Signal Processing Trends
Density
TURBO CODING
d0 or d1
n
E PRML, GEnPRML
EPRML
PARITY CODING
PRML
d0
(1,7)
(2,7)
PEAK DETECT
MFM
ANALOG
DIGITAL
H. Thapar
Time
25
Current Implementation Approaches
26
Parity-Coded Channel
Detect Error
Check Parity

Data
Correct Error
Viterbi Detector
P(D)
xk
-
Error Correlate

Delay
Maximum
nk
rk
Determine Likely Error Location
27
Design Challenges
  • One of the first Systems-on-a-Chip (SoC)
  • gt 1Gb/s rate
  • Single step vs. lookahead/parallel
  • Reduced SNR, complex detection
  • Integration with controller gives opportunities
    for more powerful coding and processing
  • Iterative decoders (Turbo, LDPC)

28
Architectural Choices
  • Equalizer
  • 6-10 taps, gt1Gb/s
  • Choices of interleaving, pipelining, recoding,
    carry-save
  • Infinite speed at the expense of power

29
Architectural Choices
  • Viterbi Decoder
  • 16 32 state, trellis coded with prostprocessor
  • Radix-2 vs. Radix-4, ACS vs. CSA
  • Bit-level pipelining

30
CSA Transformation
x y
x y
a
a
b
b-a
min(xa, yb)
min(x, yb-a)a
Min(A, B)
A B
Min(A, BK)
31
Future Signal Processing
  • SNRs will continue to decrease
  • Iterative decoding
  • Can we control the byte error rate?
  • Complexity?
  • Timing recovery at low SNRs
  • Vertical recording is already back
  • Multi-track recording?

32
IBMs Advanced Storage Roadmap
33
Holographic Storage
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