Fast Postplacement Rewiring Using Easily Detectable Functional Symmetries

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Fast Post-placement RewiringUsing Easily
DetectableFunctional Symmetries
Chung-Kuan Cheng UC San Diego
Peter R. Suaris Mentor Graphics Corp.

• Chih-Wei (Jim) Chang
• Malgorzata Marek-Sadowska
• UC Santa Barbara

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Outline

• Functional Symmetry
• Implication Supergate
• Generalized Implication Supergate
• Functional Symmetry vs. Implication Supergate
• Post-placement Timing Optimization
• Conclusion
• Future Work

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Functional Symmetry

• f (...., xi, ..., xj, ...) f (..., xj, ..., xi,
  ...)
• Non-equivalence Symmetry (NES)

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Implication Supergate

• Proposed by Dr. Kun-Han Tsai in STAR-ATPG (ITC,
  99)

0
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Implication Supergate

• Proposed by Dr. Kun-Han Tsai in STAR-ATPG (ITC,
  99)

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Generalized Implication Supergate Extraction
XOR
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0
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Theorem

• Theorem Let f be a fanout-free network. (a, b)
  are symmetric if and only if both a and b are
  and-or-reachable from f or a and b are both
  xor-reachable from f.

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Example
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Implication Supergate Statistics

• On average, 27.6 of gates are covered by
  non-trivial implication supergates

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Timing Optimization

• Similar to the gate sizing problem

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Generalized Gate Sizing

• O. Coudert, Gate Sizing for Constrained
  Delay/Power/Area Optimization, TCAD, Dec. 1997

Local Neighborhood Search
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Experiment Setting

• MCNC ISCAS benchmark
• optimized by SIS script.rugged
• timing-driven mapped to a commercial 0.35 um
  standard cell library using SIS
• placed by a commercial timing-driven placer

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Experimental Setting (cont.)

• gsg use only implication-supergate based
  rewiring
• GS use only Coudert's gate sizing algorithm
• gsgGS For gates covered by non-trivial
  implication supergates, use implication
  supergate-based rewiring. Otherwise, consider
  gate sizing for that gate

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Performance Improvement
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Conclusion

• An efficient rewiring engine based on generalized
  implication supergate is proposed
• Extraction is linear time
• Extraction is only needed once
• Traditional gate sizing algorithm is also
  generalized to include rewiring
• It is shown that implication supergate-based
  rewiring and gate sizing can complement each other

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Future Work

• Y. -M. Jiang et al has shown that RAMBO and
  buffer insertion complement each other. -DAC 1997

In-Place Optimization (IPO)