Flip Flop

1
Flip Flop State Table and State Diagram
2

• So far we analyzed the behavior of SR and D
  latch.
• The truth table and the block diagram of these
  two latch are as follows

Note that in D latch output Q is equal to input D
D
Q
Q
S
Clk
Q
Q
Clk
R
3

• As seen from the block diagram of the sequential
  circuit below, it has a feedback path from the
  output of the memory element to the input of the
  combinational circuit.
• Consequently, the input of the memory or storage
  element are derived in part from the output of
  the same or other storage elements .
• When latches are used for storage elements, a
  serious difficulty arises The state transitions
  of the latches start as soon as the clock pulse
  changes to 1.
• The new state of the latch appears at the output
  while the pulse is still active
• This output is connected to the inputs of the
  latches through the combinational circuit
• If the inputs applied to the latches change while
  the clock pulse is still in l, the latch will
  respond to new values and new output state may
  occur.

Output
Input
Combinational Circuit
Memory element
Feed Back Path
Clock Pulse
4

• The result is an unpredictable situation, since
  the state of the latches may keep changing as
  long as the clock pulse stays in active level
  (stays at 1)
• The solution is to trigger the latches only
  during a signal transition. A clock pulse goes
  through two transitions from 0 to 1 and the
  return from 1 to 0 as shown below.
• Flip flops are the type of latches that state
  change occurs only during clock pulse transition.

Respond to positive level

• The positive transition is defined as positive
  edge
• The negative transition is defined as negative
  edge
• Flip flops are constructed either as positive
  edge triggered or negative edge triggered

Positive edge response
Negative edge response
5

• Edged Triggered D Flip Flop
• The construction of a D flip flop with two D
  latches and an inverter is shown below.
• The first latch is called the master and the
  second is called slave
• The circuit samples the D input and changes the
  output only at the negative edge of the clock
  pulse
• When the clock is 0, the output of the inverter
  is 1, the slave latch is enabled, and its output,
  Q, is equal to output Y.

6

• Any change in the input changes the master output
  at Y but cannot affect the slave output
• When the pulse returns to 0, the master is
  disabled and is isolated from the D input at the
  same time the slave is enabled and the value of Y
  is transferred to the output of the flip flop at
  Q
• Thus, the output of the flip flop can change only
  during the transition of the clock from 1 to 0
  (negative edge)
• The behavior of the master-slave flip flop just
  described indicates that the output may change
  only during the negative edge of the clock.
• It is also possible to design the circuit so that
  the flip flop output changes on the positive edge
  of the clock

7

• JK flip flops
• Other types of flip flops can be constructed by
  using a D flip flop and external logic
• Two flip flops widely used in the design of
  digital systems are the JK and T flip flops
• There are three operations that can be performed
  with a flip flop set it to 1, reset it to 0, or
  complement its output
• The JK flip flop performs all three operations.
• The circuit diagram of a JK flip flop constructed
  with a D flip flop and gates is shown on the next
  slide

8

• We can investigate the circuit applied to the
  input of D latch
• D JQ KQ
• When J 1 and K0, D Q Q 1. the next clock
  edge sets the output to 1.
• When J0 and K 1, D 0, the next clock edge
  resets the output to 0.
• When both jk1, D Q, the next clock edge
  complements the output
• When both jk0, D Q, the clock edge leaves the
  output unchanged

9

• As a result, J input sets the flip flop to 1, and
  the K input resets it to 0 and when both inputs
  are enabled, the output is complemented
• The graphic symbol for the JK flip flop is shown
  below

10

• T Flip Flop
• The T flip flop is a complement flip flop and can
  be obtained from a JK flip flop when inputs J and
  K are tied together. This is shown below
• When T0 (JK0), a clock edge does not change
  the output. When T1 (JK1), a clock edge
  complements the output. The complementing flip
  flop is used for designing binary counter
• T flip flop can be constructed with a D flip flop
  as shown above
• The expression for the D input is
• D T Q TQ TQ

From JK flip-flop
Graphic symbol
From D flip-flop
11

• Characteristic Table
• A characteristic table defines the logical
  properties of a flip flop
• The characteristic tables of three types of flip
  flops are presented below
• These tables define the next state as a function
  of the inputs and the present state
• Q(t) refers to a preset state prior to the
  application of a clock edge
• Q(t1) is the next state, one clock period later

T flip flop
D flip flop
JK flip flop
12

• The characteristic table for the JK flip flop
  shows that the next state is equal to the present
  state when J K 0
• This can be expressed as Q(t1) Q(t),
  indicating that the clock produces no change in
  the state
• When K1 and J0, the clock resets the flip flop
  and Q(t1)0
• When J1, K0, the flip flop sets and Q(t1)1
• When both JK1, the next state changes to the
  complement of the present state which is Q(t1)
  Q(t)
• The next state of the D flip flop is only
  dependant on the D input and independent of the
  present state. This can be expressed as Q(t1)
  D.
• The characteristic table of T flip flop has only
  two conditions. when
• T 0, clock edge does not change the state.
  When T1, clock edge complements the state of the
  flip flop

13

• Characteristic Equation
• The logical property of a flip flop has described
  in the characteristic table can also be expressed
  algebraically with a characteristic equation
• For the D flip flop, we have the equation
• Q(t1) D
• Which meant the next state of the output will be
  equal to the value of input D
• The characteristic equation for JK flip flop can
  be derived from the table or circuit. We obtain
• Q(t1) JQ KQ
• The characteristic equation for the T flip flop
  is obtained from the circuit as
• Q(t1) T Q TQ QT