EET 3350 Digital Systems Design John Wakerly Chapter 7: 7'1 7'2

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EET 3350 Digital Systems Design John Wakerly
Chapter 7 7.1 7.2

• Sequential Circuits
• Flip-Flops

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Combinational Logic Circuits

• Output set depends only on the current input set
• If the input(s) change, the output(s) may change
• History of the input behavior is not important to
  the future output behavior

n
m
binary values, an n-bit binary number
binary values, an m-bit binary number
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Sequential Logic Circuits

• Output depends on current input and history of
  past inputs
• Information about the past behavior (history) of
  the input(s) is held in memory
• Memory is finite, holding just enough
  information as defined by design specification

n
m
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Sequential Logic Circuits

• Some of the CL outputs are used to control the
  memory elements
• Outputs from the memory elements are provided as
  inputs to the CL circuit
• this is a form of feedback
• Memory may also have an external clock signal
  to control when changes can occur

n
m
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Sequential Logic Circuits

• The addition of the extra inputs and outputs
  doesnt change the basic concepts associated with
  the CL part of the circuit
• it just has more signals
• Our approach to designing the CL circuit is the
  same as always
• Need to design the memory part

n
m
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Sequential Logic Circuits

• Memory output is considered the circuits
  current state a numerical label
• State embodies all the information about the past
  needed to define the current output
• State variables, one or more bits of information
• Present state, now, waiting
• Next state, next, with clock

n
m
j
i
binary values, an i-bit or j-bit binary number
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Describing Sequential Circuits

• State diagram
• Graphical version of states, inputs, transitions
  and outputs

SL machine to recognize that the last four inputs
have been 1
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Describing Sequential Circuits

• State table
• For each current-state, specify next-state(s) as
  a function of the present inputs
• For each current-state, specify the output(s) as
  a function of the present inputs

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Describing Sequential Circuits

• State table
• Alternate format

More about states, tables and diagrams later.
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Types of Sequential Circuits

• Two major types
• Synchronous changes in the output are only
  allowed to occur in synchronization with an
  external clock signal
• Asynchronous changes in the output are allowed
  to occur whenever there is a change in the input
  signals

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Types of Sequential Circuits

• Synchronous Sequential Circuits (also called
  Clocked Sequential Circuits)
• All signals are synchronized to some master
  clock
• The memory devices respond only when activated by
  the master clock
• The most common memory device is a flip-flop
• Circuits can be designed using systematic methods
  such as
• Excitation table method
• State equation method

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Types of Sequential Circuits

• Asynchronous Sequential Circuits
• Outputs depend solely on the order in which the
  inputs change, so timing is critical
• Based on time-delay devices
• The design methods used for synchronous
  sequential circuits do not apply to asynchronous
  circuits

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Synchronous vs. Asynchronous

• Synchronous circuits have sequential elements
  whose outputs change at the same time.
• Asynchronous circuits have sequential elements
  whose outputs change at different times.
• Disadvantages of Asynchronous Circuits
• Difficult to analyze operations
• Intermediate states that are not part of the
  desired design may be generated

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Memory Elements

• Memory elements can be anything that will make a
  past value available at some future time
• Delays, e.g., a very long wire
• A device that can hold a binary value
• Memory elements are typically flip-flops
• flip-flops and latches
• Available in several varieties
• Designer chooses based on application

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Flip-Flops and Latches

• Flip-flops have a clock input and synchronous
  outputs
• Latches are asynchronous and their outputs can
  change at anytime
• May have an enable input
• Flip-flops and Latches are both a type of
  multivibrator circuit

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Multivibrator

• Multivibrators are a group of regenerative
  circuits that are used extensively in timing
  applications
• It is a wave shaping circuit which gives
  symmetric or asymmetric square wave outputs
• It has two states either stable or quasi-stable
  depending on the type of multivibrator
• Astable not stable, no stable states
• Monostable one stable state
• Bistable two stable states

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Astable Multivibrator

• An astable multivibrator is a free running
  oscillator having two quasi-stable states.
• Thus, there is oscillation between these two
  states and no external signal is required to
  produce the change in state

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Monostable Multivibrator

• A monostable multivibrator is one which generates
  a single pulse of specified duration in response
  to each external trigger signal.
• It has only one stable state.
• Application of a trigger causes a change to the
  quasi-stable state.

1
0
1
0
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Bistable Multivibrator

• A bistable multivibrator is one that maintains a
  given output voltage level unless an external
  trigger is applied.
• Application of an external trigger signal causes
  a change of state, and this output level is
  maintained indefinitely until an second trigger
  is applied .
• Thus, it requires two external triggers before it
  returns to its initial state

1
1
0
0
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Multivibrator Types

• Mechanical analogy

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Clock Signal Parameters

• Very important with most sequential circuits
• State variables change state at clock edge.

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Bistable Elements

• The simplest sequential circuit (note feedback)
• Two states
• One state variable, say, Q

HIGH
LOW
Q Stable at 0
LOW
HIGH
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Bistable Elements

• The simplest sequential circuit (note feedback)
• Two states
• One state variable, say, Q

LOW
HIGH
Q Stable at 1
HIGH
LOW
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Analog Analysis

• Assume pure CMOS thresholds, 5.0 V rail
• Theoretical threshold center is 2.5 V

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Analog Analysis

• Assume pure CMOS thresholds, 5.0 V rail
• Theoretical threshold center is 2.5 V

2.5 V
2.5 V
2.5 V
2.5 V
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Analog Analysis

• Assume pure CMOS thresholds, 5.0 V rail
• Theoretical threshold center is 2.5 V

2.5 V
2.5 V
2.51 V
4.8 V
0.0 V
Q Stable at 0
2.5 V
2.5 V
4.8 V
0.0 V
5.0 V
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Metastability

• Metastability is inherent in any bistable circuit
• Two stable points, one metastable point

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Another Look at Metastability

• Another mechanical analogy for metastability

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Teeter-Totter Behavior
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Why Worry About Metastability?

• All real systems are subject to it
• Problems are caused by asynchronous inputs that
  do not meet flip-flop setup and hold times
• Details in Chapter-7 flip-flop descriptions and
  in Section 8.9 (later in semester)
• Especially severe in high-speed systems
• since clock periods are so short, metastability
  resolution time can be longer than one clock
  period
• Many digital designers, products, and companies
  have been burned by this phenomenom

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Back to the Bistable Circuit

• How to control it?
• add control inputs
• S-R latch

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S-R Latch Operation
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S-R Latch Timing Parameters

• Propagation delay
• Minimum pulse width

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S-R Latch Symbols
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S-R Latch Using NAND Gates
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S-R Latch With Enable
EN
EN
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D Latch or Data Flip-Flop
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D Latch Operation
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D Latch Timing Parameters

• Propagation delay (from C or D)
• Setup time (D before C edge)
• Hold time (D after C edge)

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Edge-Triggered D Flip-Flop Behavior
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D Flip-Flop Timing Parameters

• Propagation delay (from CLK)
• Setup time (D before CLK)
• Hold time (D after CLK)

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TTL Edge-Triggered D F-F Circuit

• Preset and clear inputs
• like S-R latch
• 3 feedback loops
• interesting analysis
• Light loading on D and C

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CMOS Edge-Triggered D F-F Circuit

• Two feedback loops (master and slave latches)
• Uses transmission gates in feedback loops
• Interesting analysis method (Sec. 7.9)

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Other D Flip-Flop Variations

• Negative-edge triggered

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Scan Flip-Flops Used for Testing

• TE 0 gt normal operation
• TE 1 gt test operation
• All of the flip-flops are hooked together in a
  daisy chain from external test input TI.
• Load up (scan in) a test pattern, do one normal
  operation, shift out (scan out) result on TO.

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J-K Flip-Flops
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T or Toggle Flip-Flops

• Important for counters

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Flip-Flop Excitation Tables

• Use these to move to next state
• Used to design the memory control CL circuit

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Flip-Flop Excitation Tables