Minimizing Leakage Power in Sequential Circuits by Using Mixed Vt FlipFlops

1
Minimizing Leakage Power in Sequential Circuits
by Using Mixed Vt Flip-Flops

• Jaehyun Kim and Youngsoo Shin
• Dept. of Electrical Engineering, KAIST, KOREA

2
Outline

• Introduction
• Motivation
• Design of mixed Vt flip-flops
• Allocation algorithm mixed Vt flip-flops and
  dual Vt gates
• Experimental results
• Conclusion

3
Growth of Leakage Current
Active
Current (A)
Leakage
Year
Intel Corporation, 2005
4
Leakage Control

• Active leakage
• Dual Vt, dual Tox
• Selective MTCMOS
• IVC (input vector control)
• Zigzag power gating
• Standby leakage
• Power gating
• Adaptive body bias
• Dynamic voltage scaling

task
t
active
active
standby
5
Dual Vt

• Dual Vt
• Can be integrated seamlessly into conventional
  design flow
• Reduce both active and standby leakage
• Dual Vt allocation
• Critical path ? Low Vt (fast, large leakage)
• Non-critical ? High Vt (slow, small leakage)

6
Motivation

• Limitation of conventional dual Vt
• Allocates dual Vt only to combinational gates

Dual Vt
Need to reduce flip-flop leakage
7
Dual Vt Flip-Flops

• High Vt flip-flop
• Small leakage
• But, significant increase of delay (Tsu and Tc-q)

8
Dual Vt Flip-Flops

• High Vt flip-flop
• Small leakage
• But, significant increase of delay (Tsu and Tc-q)

5
0
0
5
0
0
Leakage (pA)
Delay (ps)
4
0
0
4
0
0
3
0
0
3
0
0
2
0
0
2
0
0
1
0
0
1
0
0
0
0
LVT
HVT
LVT
HVT
9
Our Approach

• Mixed Vt flip-flops
• MVT-I Tsu increases, Tc-q remains the same
• MVT-II Tsu remains the same, Tc-q increases
• Consume slack at only one side (D or Q)
• Allocation algorithm
• Determine the types of gates F/Fs collectively
  based on leakage-delay sensitivity
• 2 types of comb. gates
• 4 types of flip-flops

LVT, HVT
LVT, HVT, MVT-I, MVT-II
10
Mixed Vt Flip-Flops

• Mixed Vt flip-flop I (MVT-I)
• Slightly smaller leakage than LVT flip-flop
• Tsu increases, but Tc-q remains the same

11
Mixed Vt Flip-Flops

• Mixed Vt flip-flop I (MVT-I)
• Slightly smaller leakage than LVT flip-flop
• Tsu increases, but Tc-q remains the same

200
5
0
0
Leakage (pA)
Delay (ps)
4
0
0
150
3
0
0
100
2
0
0
50
1
0
0
0
0
LVT
MVT-I
LVT
MVT-I
12
Mixed Vt Flip-Flops

• Mixed Vt flip-flop II (MVT-II)
• Greatly smaller leakage than LVT flip-flop
• Tsu doesnt increase, and only Tc-q increases

g1
13
Mixed Vt Flip-Flops

• Mixed Vt flip-flop II (MVT-II)
• Greatly smaller leakage than LVT flip-flop
• Tsu doesnt increase, and only Tc-q increases

5
0
0
3
5
0
Leakage (pA)
Delay (ps)
3
0
0
4
0
0
2
5
0
3
0
0
2
0
0
1
5
0
2
0
0
1
0
0
1
0
0
5
0
0
0
LVT
MVT-II
LVT
MVT-II
14
Mixed Vt Flip-Flops

• Comparisons of leakage and delay
• 90-nm commercial process

3
5
0
5
0
0
Leakage (pA)
Delay (ps)
3
0
0
4
0
0
2
5
0
3
0
0
2
0
0
1
5
0
2
0
0
1
0
0
1
0
0
5
0
0
0
LVT
HVT
MVT-I
MVT-II
LVT
HVT
MVT-I
MVT-II
MVT-I MVT-II can be utilized where HVT cant
15
Allocation Algorithm

• Given
• A technology-mapped netlist
• Timing constraints (ATs, RATs, cycle time)
• Gate library
• 2 types for each comb. gate (LVT, HVT)
• 4 types for each flip-flop (LVT, HVT, MVT-I,
  MVT-II)
• Goal
• Find allocations which,
• Minimize leakage current
• While satisfying timing constraints

16
Allocation Algorithm

• Key idea
• Initially allocate HVT to each gate
• Select a gate having the min cost ( min
  sensitivity)
• Allocate LVT (or MVTs if F/Fs) to it
• Repeat 23, until no negative path remains
• Concept of sensitivity
• Represents the leakage penalty over timing
  improvement
• Defined differently for comb. gates and F/Fs

17
Allocation Algorithm

• Sensitivity of a comb. gate Karnik, DAC02

ignore non-negative paths
path 1 (5)
High Vt
path 2 (0)
A
Z
B
path 3 (-5)
20
leakage
path 4 (-10)
i index of a gate
p a timing path
dip delay of gate i in path p
sip slack of gate i in path p
18
Allocation Algorithm

• Sensitivity of a comb. gate

HVT ? LVT
?d(A) 8 ?d(B) 7
A
slack
Z
B
path 3 (-5)
path 3 (-5 ? 3)
path 3 (-5 ? 3)
20 ? 220
leakage
path 4 (-10)
path 4 (-10 ? -3)
path 4 (-10 ? -3)
19
Allocation Algorithm

• Sensitivity of a flip-flop

90
leakage
High Vt
D
Q
CK
path 1 (10)
path 1 (10)
path 2 (-30)
path 2 (-30)
path 2 (-30)
path 3 (-25)
path 3 (-25)
20
Allocation Algorithm

• Sensitivity of a flip-flop

HVT ? MVT-I
90 ? 1000
leakage
?Tsu 5 ?Tc-q 20
D
Q
CK
slack
path 2 (-30)
path 2 (-30 ? -5)
path 2 (-30 ? -5)
path 3 (-25)
path 3 (-25 ? -5)
path 3 (-25 ? -5)
21
Allocation Algorithm

• Sensitivity of a HVT flip-flop
• HVT flip-flop can be replaced by LVT, MVT-I, or
  MVT-II
• So, compute three sensitivities for every
  candidate (LVT, MVT-I, MVT-II)
• Then, choose the minimum as a representative
• Sensitivity of a MVT flip-flop
• MVT flip-flop can be replaced only by LVT
• So, its sensitivity is from MVT to LVT

22
Allocation Algorithm

• Pseudo code
• Allocate high Vt to each gate
• Perform STA
• Compute sensitivity of each gate
• while ( of negative slack paths gt 0 )
• Select a minimum sensitivity gate
• Allocate the corresponding Vt type to the gate
• Perform incremental STA
• Update sensitivities of affected gates

23
Experiment

• Experimental setup
• Prototype implemented in SIS
• Experiments with ISCAS ITC benchmarks
• Commercial 90-nm technology RVT and HVT
• Conventional
• Combinational gates ? Dual Vt
• Sequential elements ? Low Vt only
• Use sensitivity-based algorithm Karnik, DAC02
• Proposed
• Combinational gates ? Dual Vt
• Sequential elements ? Dual Vt mixed Vt
• Use proposed algorithm

24
Experimental Results
25
Comparison with ILP

• Proposed vs. ILP
• ILP can produce the optimum for small circuit
• Almost the same results (difference 3)

1.0
Normalized leakage
0.8
0.6
proposed
ILP
0.4
0.2
0.0
s298
s400
s641
s838
b03
b07
b08
b09
26
Slack Histograms

• s838 benchmark circuit
• Negative impact on yield is marginal

100
80
60
Mixed Vt flip-flops Dual Vt (proposed)
40
Dual Vt (conventional)
20
All low Vt (unoptimized)
0
0
100
200
300
400
500
600
700
800
Slack ps
27
Conclusion

• Mixed Vt flip-flops
• Have increased delay either on Tsu or Tc-q
• ? Can be utilized where HVT F/F cant
• Propose new heuristic algorithm
• Based on leakage-delay sensitivity
• Allocate mixed Vt flip-flops as well as dual Vt
  gates
• Result (compared to the conventional)
• Average 57 flip-flop leakage saving
• Average 31 total leakage saving

28
Q A
Thank you for your attention !