Enabling Technologies for Reconfigurable Computing and Software Configware CoDesign Part 3: Resource

1
Enabling Technologies for Reconfigurable
Computing and Software / Configware Co-Design
Part 3Resources for RC-
July 8, 2002, ENST, Paris, France

• Reiner Hartenstein
• University of
• Kaiserslautern

2
Schedule
3
Opportunities by new patent laws ?

• to clever guys being keen on patents
• dont file for patent following details !
• everything shown in this presentation has been
  published years ago

4
gtgt Configware Industry

• Configware Industry
• Terminology
• MoPL data-procedural language
• Anti architecture and circuitry
• Stream-based Memory Architecture

http//www.uni-kl.de
5
Configware heading for mainstream

• Configware market taking off for mainstream
• FPGA-based designs more complex, even SoC
• No design productivity and quality without good
  configware libraries (soft IP cores) from various
  application areas.
• Growing no. of independent configware houses
  (soft IP core vendors) and design services
• AllianceCORE Reference Design Alliance
• Currently the top FPGA vendors are the key
  innovators and meet most configware demand.

6
OS for PLDs

• separate EDA software market, comparable to the
  compiler / OS market in computers,
• Cadence, Mentor, Synopsys just jumped in.
• lt 5 Xilinx / Altera income from EDA SW

7
Xilinx Alliances

• The Software AllianceEDA Program
• ... Xilinx Inc.'s Foundation...
• free WebPACK downloadable tool palette

• The Xilinx XtremeDSP Initiative (with Mentor
  Graphics)
• MathWorks / Xilinx Alliance.
• The Wind River / Xilinx alliance

8
The Software Alliance EDA Program
IKOS Systems, Innoveda, Mentor Graphics,
MiroTech, Model Technoloy, Protel
International, Simucad, SynaptiCAD,
Synopsys, Synplicity, Translogic, Virtual
Computer Corporation.

• Acugen Software,
• Agilent
• EEsof EDA,
• Aldec,
• Aptix,
• Auspy Development,
• Cadence,
• Celoxica,
• Dolphin Integration,
• Elanix,
• Exemplar,
• Flynn Systems,
• Hyperlynx,

• provides a wide selection of EDA tools

helps leading EDA vendors to integrate Xilinx
Alliance software tightly into their tools
9
The Xilinx AllianceCORE program

• a cooperation between Xilinx and third-party core
  developers, to produce a broad selection of
  industry-standard solutions for use in Xilinx
  platforms. - Partners are

Amphion Semiconductor, Ltd. ARC Cores CAST,
Inc. DELTATEC Derivation Systems, Inc. Dolphin
Integration (Grenoble) Eureka Technology Inc.
Frontier Design Inc. GV Associates, Inc.
inSilicon Corporation iCODING Technology Inc.
Loarant Corporation Mindspeed Technologies - A
Conexant Business (formerly Applied Telecom)
MemecCore Mentor Graphics Inventra NewLogic
Technologies, Inc. (Europe) NMI Electronics
Paxonet Communications, Inc. Perigee, LLC
Rapid Prototypes Inc. sci-worx GmbH (Hannover,
Germany) SysOnChip TILAB (Telecom Italia Lab)
VAutomation Virtual IP Group, Inc. XYLON.
10
The Xilinx Reference Design Alliance Program

• The Xilinx Reference Design Alliance Program
  helps the development of multi-component
  reference designs that incorporate Xilinx devices
  and other semiconductors.
• The designs are fully functional, but no
  warranties, no liability. Partners are.

JK microsystems, Inc. LYR Technologies NetLogic
Microsystems
ADI Engineering Innovative Integration
11
The Xilinx University Program

• The Xilinx University Program provides
• Xilinx Student Edition Software,
• Professor Workshops,
• a Xilinx University User Group,
• Presentation Materials and Lab Files,
• Course Examples,
• Research,
• Books, etc.

12
Altera offers over a hundred IP cores (1)
Altera offers over a hundred IP cores like, for
example

• modulator,
• synchronizer,
• DDR SDRAM controller,
• Hadamar transform,
• interrupt controller,
• Real86 16 bit microprocessor,
• floating point,
• FIR filter,
• discrete cosine,
• ATM cell processor,
• and many others.

• controller,
• UART,
• microprocessor,
• decoder,
• bus control,
• USB controller,
• PCI bus interface,
• viterbi controller,
• fast Ethernet
• MAC receiver or transmitter,

13
Altera offers over a hundred IP cores (2)

• from Altera
• AMIRIX Systems, Inc.
• Amphion Semiconductor, Ltd.
• Arasan Chip Systems, Inc.
• CAST, Inc.
• Digital Core Design
• Eureka Technology Inc.
• HammerCores
• Innocor
• Ktech Telecommunications, Inc.
• Lexra Computing Engines
• Mentor Graphics - Inventra

Modelware Ncomm, Inc. NewLogic Technologies
Northwest Logic Nova Engineering, Inc.
Palmchip Corporation Paxonet Communications
PLD Applications Sciworx Simple Silicon
Tensilica TurboConcept.
14
Altera IP core design services

• Altera IP core design services are available from

• Northwest Logic

15
Altera Certified Design Center (CDC) Program

• Certified Design Center (CDC) Program
• Barco Silex
• El Camino GmbH
• Excel Consultants
• Plextek
• Reflex Consulting
• Sci-worx
• Tality
• Zaiq Technologies.

16
The Altera Consultants Alliance Program (ACAP)

• The Altera Consultants Alliance Program (ACAP)
  lists
• 41 offices in North America and
• 29 in the rest of the world.

17
Devlopment boards

• Devlopment boards are offered from
• Altera
• El Camino GmbH
• Gid'el Limited
• Nova Engineering, Inc.
• PLD Applications
• Princeton Technology Group
• RPA Electronics Design, LLC
• Tensilica.

18
Consultants and services not listed by Xilinx
nor Altera (index)
Flexibilis, Tampere, Finland, Geoff Bostock
Designs, Wiltshire, England, Great River
Technology, Alberquerque, NM, New Horizons GB
Ltd, United Kingdom, North West Logic Silicon
System Solutions, Canterbury, Australia,
Smartech, Tampere, Finland, Tekmosv, Austin,
Texas, The Rockland Group, Garden Valley,
CA Nick Tredennick, Los Gatos, California,
Vitesse,

• Algotronix, Edinburgh,
• Andraka Consulting Group
• Arkham Technology, Pasadena, CA
• Barco Silex, Louvain-la-Neuve, Belgium,
• Bottom Line Technologies, Milford, NJ
• Codelogic, Helderberg, South Africa,
• Coelacanth Engineering, Norwell, MASS
• Comit Systems, Inc., Santa Clara, CA
• EDTN Programmable Logic Design Center

19
Consultants and services not listed by Xilinx
nor Altera (1)

• Algotronix, Edinburgh, Reconfigurable Computing
  and FPL in software radio, communications and
  computer security
• Andraka Consulting Group high performance FPGA
  designs for DSP applications
• Arkham Technology, Pasadena, low cost IP cores
  for Xilinx and Atmel, embedded processor, DSP,
  wireless communication, COM / CORBA / DirectX,
  client-server database programming, software
  internationalization, PCB design
• Barco Silex, Louvain-la-Neuve, Belgium, IP
  integration boards for ASIC and FPGA,
  consultancy, design, sub-contracting

20
Consultants and services not listed by Xilinx
nor Altera (2)

• Bottom Line Technologies, Milford, New Jersey,
  FPGA design, training, designing Xilinx parts
  since 1985
• Codelogic, Helderberg, South Africa, consulting,
  FPGA design services
• Coelacanth Engineering, Norwell, Massachusetts,
  design services, test development services, in
  wireless communication, DSP-based
  instrumentation, mixed-signal ATE
• Comit Systems, Inc., Santa Clara, California,
  DSP, ASIC, networking, embedded control in
  avionics -- FPGA / ASIC design and system
  software
• EDTN Programmable Logic Design Center

21
Consultants and services not listed by Xilinx
nor Altera (3)

• FirstPass, Castle Rock, Colorado
• Vitesse, ASIC design
• Flexibilis, Tampere, Finland, VHDL IP cores for
  Xilinx products
• Geoff Bostock Designs, Wiltshire, England, FPGA
  design services
• Great River Technology, Alberquerque, New Mexico,
  FPGA design services in digital video and
  point-to-point data transmission for aerospace,
  military, and commercial broadcasters
• New Horizons GB Ltd, United Kingdom, FPGA design
  and training, Xilinx specialist
• North West Logic FPGA and embedded processor
  design in digital communications, digital video

22
Consultants and services not listed by Xilinx
nor Altera (4)

• Silicon System Solutions, Canterbury, Australia,
  VHDL IP cores for the ASIC and FPGA/CPLD/EPLD
  markets
• Smartech, Tampere, Finland, ASIC and FPGA design
• Tekmosv, Austin, Texas, Multiple Designs on a
  Single Gate Array, HDL synthesis, design
  conversions, chip debug, test generation
• The Rockland Group, Garden Valley, California, a
  TeleConsulting organization about logic design
  for FPGAs
• Nick Tredennick, Los Gatos, California, investor
  and consultant

23
gtgt Terminology

• Configware Industry
• Terminology
• MoPL data-procedural language
• Anti architecture and circuitry
• Stream-based Memory Architecture

http//www.uni-kl.de
24
Terminology
25
Terminology Acronyms

• RC reconfigurable computing
• RL reconfigurable logic

• Software (SW) procedural sources
• Configware (CW) structural sources
• Hardware (HW) hardwired platforms
• ASIC customizable hardwired platforms
• Flexware (FW) reconfigurable platforms
• FPGA field-programmable gate array
• FPL field-programmable logic

) note firmware is SW !
26
Stream-based Computing (2)
terms

• DPU datapath unit
• DPA datapath array
• rDPU reconfigurable DPU
• rDPA reconfigurable DPA

• stream-based computing using complex pipe
  network (super-systolic Kress et al.)

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Confusing Terminology

• Computer Science and EE as well as ist RD and
  applicatgion areas suffer from a babylonial
  confusion.
• Communication not only between Computer Science
  and EE, but also between ist special areas, even
  between ist different abstrac tion levels is made
  difficult mainly because of immature
  terminology in relation to reconfigurable
  circuits and their applications.
• Terms are rarely standardized and often used with
  drastically different meanings even within then
  same special area.
• Often terms have been so badly coined, that they
  are not self-explanatory, but mesleading. A
  demonstratory example is the comparizon of terms
  used used in VHDL and Verilog.  
• Ideal are "intuitive" terms. But often Intuition
  yields the wrong idea. Whenever a new term
  appears in teaching, I often have to tell the
  students, that the term does not mean, what he
  believes.  

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Terms (1)
.  
à la Ingo Kreuz
   
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Terms (2)
.  
à la Ingo Kreuz
   
30
Terms (3)
.  
à la Ingo Kreuz
   
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Hardware Terms (1)
 
à la Ingo Kreuz
) processing datastreams (transport-triggered),
not yet a machine autosequencing memory missing
 
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Hardware Terms (2)
 
à la Ingo Kreuz
 
33
Terms on Parallelism (1)
 
à la Ingo Kreuz
 
34
Terms on Parallelism (2)
 
à la Ingo Kreuz
 
35
Terms on Parallelism (3)
 
à la Ingo Kreuz
 
36
Counterparts
à la Ingo Kreuz
 
37
gtgt MoPL data-procedural language

• Configware Industry
• Terminology
• MoPL data-procedural language
• Anti architecture and circuitry
• Stream-based Memory Architecture

http//www.uni-kl.de
38
Fundamental Ideas available (1)

• Data Sequencer Methodology
• Data-procedural Languages (Duality with v N)
• ... supporting memory bandwidth optimization
• Soft Data Path Synthesis Algorithms
• Parallelizing Loop Transformation Methods
• Compilers supporting Soft Machines
• SW / CW Partitioning Co-Compilers

39
Fundamental Ideas available (2)

• Programming Xputers
• Similarities to programming computers
• How not to get confused by similarities
• What benefits vs. Computers ?

40
Programming Language Paradigms
easy to learn
41
Similar Programming Language Paradigms
very easy to learn
42
JPEG zigzag scan pattern
published in 1993
43
gtgt Anti architecture and circuitry

• Configware Industry
• Terminology
• MoPL data-procedural language
• Anti architecture and circuitry
• Stream-based Memory Architecture

http//www.uni-kl.de
44
GAU generic address unit Scheme
published in 1990
GAU
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GAG Address Stepper
GAG Address Stepper
published in 1990
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Generic Sequence Examples
atomic scan
linear scan
video scan
-90º rotated video scan
-45º rotated (mirx (v scan))
sheared video scan
non-rectangular video scan
zigzag video scan
spiral scan
feed-back-driven scans
perfect shuffle
published in 1990
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Slider Animation Demo
published in 1990
address
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GAG Complex Sequencer Implementation
all been published in 1990
Generic Address Generator
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gtgt Stream-based Memory Architecture

• Configware Industry
• Terminology
• MoPL data-procedural language
• Anti architecture and circuitry
• Stream-based Memory Architecture

http//www.uni-kl.de
50
MoM Xputer Architecture
published in 1990
51
Antimachine MoM architecture
52
Linear Filter Application
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Scanline unrolling
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90o Rotation of Scan Pattern
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Linear Filter Application
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XMDS Scan Pattern Editor GUI
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MoM Architecture Features

• Scan Cache Size adjustable at run time
• Any other shape than square supported
• 2-dimensional memory space
• Supports generic scan patterns
• Subject of parallel access transformations
• compare Francky Cathoor et al .
• Supports visualization

58
Hot Research Topic Memory Architectures

• High Performance Embedded Memory Architectures
  Cathoor et al.
• High Performance Memory Communication
  Architectures Herz
• Custom Memory Management Methodology Cathoor et
  al
• Data Reuse Transformations Kougia et al.
• Data Reuse Exploration Soudris, Wuytak
• Rapidly greowing market IP cores, module
  generators ets.

59
Processor Memory Performance Gap
von Neumann bottleneck
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rDPAs classical cache does not help

• super pipe networks, no parallel computers !

• Stream-based arrays are a memory bandwidth problem

• the memory bandwidth problem is often more
  dramatic then for microprocessors

• classical interleaving is not practicable, since
  based on sequential instruction streams

however, the anti machine has no vN bottleneck!

• classical caches do not help, since instruction
  sequencing is not used

• the problem throughput of parallel data streams,
  not instruction streams

61
Data-Stream-based Soft Anti Machine
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The Disk Farm? or a System On a Card?
Gordon Bell, Jim Gray, ISCA2000

• The 500GB disc card
• LOTS of bandwidth
• A few disks replaced by
• gt10s Gbytes RAM
• and a processor

MicroDrive1.7 x 1.4 x 0.2 2006 ? 1999 340
MB, 5400 RPM, 5 MB/s, 15 ms seek 2006 9 GB, 50
MB/s ? (1.6X/yr capacity, 1.4X/yr
BW) Integrated IRAM processor 2x height Connected
via crossbar switch growing like Moores law 16
Mbytes 1.6 Gflops 6.4 Gops 10,000 nodes in
one rack! 100/board 1 TB 0.16 Tflops
63
MoM Application Examples

• Image Processing
• Grid-based design rule check 1983
• 4 by 4 word scan cache
• Pattern-matching based
• Our own nMOS DPLA design
• design rule violation pixel map automatically
  generated from textual design rules
• 256 MC nMOS, 800 single metal CMOS
• Speed-up gt 10000 vs. Motorola 68000

) machine not yet discovered
64
Schedule
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gtgtgt Coarse Grain
- END -
66
Schedule
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Synthesizable Memory Communication
http//kressarray.de
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Memory Communication Architecture

• hot research topic in embedded systems
• storage context transformations Herz, others
• for low power
• for high performance
• startups provide memory IP or generators