GP256 Graphics Coprocessor

1
GP256 Graphics Co-processor

• ELEC 422 VLSI Design I
• Alex Chen
• Jake Schneider
• Lauren Schiff
• Erik Welsh

2
Outline

• Functional Description and Project Status
• Registers and Multiplexors
• FSM Controller
• Address Generation Unit
• ALU
• System Performance
• Floorplan and Cell Hierarchy

3
Functional Description

• Graphics Co-Processor
• 6 Image Processing Functions
• 16x16 Grayscale Image
• Features
• Status

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Registers
5
Muxes
The three input mux (at right) is comprised of
three t-gates and three inverters. The three
input muxes are used to regulate the input to
register A, while the two input muxes are used on
register B and ACC.
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Main Controller Summary

• ALU Control
• OpCode
• Memory Control
• Read/Write signals
• Index offset bits
• Increment
• Register Control
• Latch signals
• Clear signals
• Enable signals

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Finite State Machine Transitions
Invert
Min
Max
Smooth
FlipV
FlipH
INIT
A ?255 B ?Pixel
Load Pixels
Load Pixels
Load Adjacent Pixels
Load Pixel
Load Pixel
Add
Acc?A-B
Find Min
Find Max
Flip Row
Flip Col
Shift by 2
Add
Shift by 1
Store
Last Pix?
No
Yes
Stop
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Irsim Results for Smoothing
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Address Generation Unit

• Functions
• Flip Row or Column
• Generate Addresses (Right)
• ALU
• Separate 4-bit adders
• Unified 8-bit adder
• Separate Memory Controller
• Handshake with Main PLA
• Control Signals

Memory Addresses of Pixels for Min, Max, and
Smoothing
R0 Memi R1 Memi 1 R2 Memi - 16 R3
Memi - 1 R4 Memi 16
R4
R3
R0
R1
R2
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Block Diagram of AGU
8-bit Reg.
8-bit Reg.
4-bit Adder
4-bit Adder
T-gates
From Controller
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ALU

• 10-bit ripple-carry adder
• Subtraction
• Division
• Comparator

Single Bit Adder Cell
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Full System Timing Analysis
Main PLA
Address Gen. Unit
AGU PLA
VA3SB3
VB1SA2
VB2SA3
QA2
QB2
10 Bit Reg. A
10 Bit Reg. Acc
10 Bit Reg. B
VA2SB2
VA1
ALU
VA2
VB2SA3
VA2SB2
VA2SB2
VB2SA3
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Timing Analysis
Max clock rate 14 Mhz
Longest Path 24 ns R/W access 70 ns
ALU Spice Analysis
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Floorplan