Optics and Routing for the Internet

1
Optics and Routing for the Internet

• Steve Wallach
• swallach_at_chiaro.com

2
Presentation Outline

• Fundamental Laws- Physics
• Trends in Telecommunications
• Trends in Router Architecture
• Interaction with the Internet
• Vision
• Computer Stuff
• Conversion LAN/WAN/SAN

3
Fundamental Laws

• C - Speed of light
• Power Consumption
• Propagation Delay

4
POWER CONSUMPTION

• C capacitance
• V voltage
• F frequency

5
PROPAGATION DELAY

• Lossless Line
• Lossly Line

6
OTHER CONSTRAINTS

• Cost of Investment - I (billions)
• Size of Market - M (millions)
• LHospitals Rule of Profit
• Profit dM/dI
• as I approaches infinity
• as M approaches K (sometimes 0)
• result is 1 (success) 0 (failure)
• The government uses different rules

7
Trends in Telecommunications

• Advances in PHOTONIC (mainly WDM) technology.
• TERAHZ (THz) requirements
• All optical networks (AON)
• Effect on digital computer architecture
• The next interconnect topology
• www.ll.mit.edu/aon/
• Lemott, et. al., low-cost WDM, Aug. 97, IEEE
  summer topicals, Montreal.

8
WDM ARCHITECTURE
9
WDM ARCHITECTURE
10
TECHNOLOGY
11
WDM IMPLEMENTATION
12
Trends in Router Architecture

• Mckeowns Four Generations
• How does one implement the 4th. Generation
• Do we need a 4th. Generation router?

13
First Generation Routers
Fixed length DMA blocks or cells. Reassembled
on egress linecard
Shared Backplane
Line Interface
Fixed length cells or variable length packets
Typically lt0.5Gb/s aggregate capacity
14
Second Generation Routers
CPU
Buffer Memory
Route Table
Line Card
Line Card
Line Card
Drop Policy Or Backpressure
Drop Policy
Buffer Memory
Buffer Memory
Buffer Memory
Fwding Cache
Fwding Cache
Output Link Scheduling
MAC
MAC
MAC
Typically lt5Gb/s aggregate capacity
15
Third Generation Routers
Switched Backplane
Line Card
CPU Card
Line Card
Local Buffer Memory
Local Buffer Memory
Line Interface
CPU
Routing Table
Memory
Fwding Table
MAC
MAC
Typically lt50Gb/s aggregate capacity
16
Fourth Generation Routers/Switches
Optical links
100s of feet
Switch Core
Line cards
17
Fourth Generation Routers/SwitchesQueuing
Structure
Virtual Output Queues
1 read per cell time
1 write per cell time
Lookup Drop Policy
Output Scheduling
Switch Fabric
Lookup Drop Policy
Output Scheduling
Switch Arbitration
Lookup Drop Policy
Output Scheduling
Switch Core (Buffer less)
Linecard
Linecard
Typically lt5Tb/s aggregate capacity
18
Questions on 4th Generation Router

• What technology can be used for the switch
• Electronics
• Optics
• What are the design objectives?
• Can the router be ALL-Optical?

19
Some General Guidelines

• If the internet is based on TCP/IP and packets as
  defined by IPV(46), then the packet switched
  net will not be all optical
• Decode packet headers (optical memory)
• Decode various control fields
• If packet classification is required then the
  packet switched net will not be all optical
• Source/destination identification
• Distributed denial of service attacks

20
Some Problem Areas

• RefW. Bux, et. al, Technologies and Building
  Blocks for fast packet forwarding, IEEE
  Communications Magazine, January, 2001

21
Optics The Preferred Interconnect
www.hpcc.gov/talks/petaflops-24june97
22
Design Objectives 4th. Generation

• Must support packet processing at line speed
• Must support OC192c and OC768c
• Must be scalable in the field to 100s (if not
  1000s of ports)
• Must be reliable and fit into normal CO
  environment (NEBS and Bellcore)
• Must be CISCO Compatible?

23
Design Objectives

• Must be able to be designed
• The software must be able to be developed
• The reliability must be in the 6 9s.
• Otherwise you could lose half the country
• Using the 4th. Generation model
• How do you do arbitration for a buffer less
  switch
• How do you switch OC768, 40 byte packets (less
  than 10 ns/packet)
• How do you look up 40 byte packets at line speed
• How to do you provide security against
• Distributed Denial of Service
• Password Attacks
• Etc, etc, etc

24
Electronic Solutions

• Avici (www.avici.com)
• Electrical Hypercube
• Pluris (www.pluris.com)
• Parallel Optics to Electrical Switch
• Clusters of smaller routers (router farms)
• Use OC192 and Ethernet to build larger routers

25
Optical Switching

• Space Switching
• Mems (www.omminc.com)
• Lithium Niobate
• SOAs
• Waveguide
• LCDs
• Holographic
• Time Switching
• Tunable Lasers (wdm.stanford.edu/hornet)
• Ref journal of lightwave technology, june
  1996, vol 14, special issue on multiwavelength
  optical technology and networks. Many good papers

26
Which one to use

• Cost
• Optical Characteristics
• dB loss
• Cross Talk
• Bellcore Specs
• Must be semi-conductor based
• Application
• Cross Connect
• Packet Switch
• Add/Drop Mux

27
More

• If buffer less, (ref, Mckeown 4th generation)
• How does one schedule 100s (1000s of inputs)
• Central scheduler
• CSMA/CS (ala hornet)
• How is the signal encoded
• Clock/Data Recovery (PLLs/DLLs)
• What error codes to use
• What BER is sufficient
• Burst optics

28
Cross Connects

• ALL OPTICAL Groom Channels
• No conversion from optical to electrical
• Generally uses MEMS
• Also tunable laser
• Sonet Recovery Time driving switching speed (50
  milliseconds originally derived from DS1 DS3
  multiplexer recovery time)
• Calient, Luxcore, Tellium, etc
• Will MPLS replace cross connect?

29
Computer Stuff

• Computers and Telecommunications are converging
• Optics for chip to chip connect
• Still need fast and efficient burst transmission
• Optics is higher bandwidth and can drive longer
  distances
• WDM techniques can be used

30
INTEGRATED SMP - 4 CPU
DRAM - 4 GBYTES - HIGHLY INTERLEAVED
2.5 ghz 80 gbytes/sec 256 pins/bus
BUS 1
...
CROSS BAR
BUS N
coherence
2nd LEVEL CACHE 96 MBYTES
64 bytes wide
64 bytes wide
160 gbytes/sec
160 gbytes/sec
VLIW/RISC CORE 24 GFLOPS 6 ghz
...
31
INTEGRATED SMP - WDM
DRAM - 4 GBYTES - HIGHLY INTERLEAVED
MULTI-LAMBDA AON
CROSS BAR
coherence
640 GBYTES/SEC
2nd LEVEL CACHE 96 MBYTES
64 bytes wide
160 gbytes/sec
VLIW/RISC CORE 24 GFLOPS 6 ghz
...
32
COTS Router/PetaFlop SystemGeneral Purpose
Packet Processor
128 die/box 4 CPU/die
3
4
...
5
2
16
1
17
64
ALL-OPTICAL SWITCH
18
63
...
...
32
49
48
Multi-Die Multi-Processor
...
33
47
46
I/O
10 meters 50 NS Delay
LAN/WAN
33
High-port Count, Non-blocking All-optical Switch
With Nanosecond Switching Speed.
34
CONFIRMATION?

• Our 2010 CPU will operate on the same principle
  as todays PCs. But instead of electronic
  microprocessors providing the brains and brawn,
  our future CPU will have optoelectronic
  integrated circuits (silicon to switch, but
  optics to communicate).
• REF. Forbes, ASAP section, page 88, August 21,
  2000.