The Importance of Adopting a PackageAware Chip Design Flow

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R I O D E S I G N A U T O M A T I O N
The Importance of Adopting aPackage-Aware Chip
Design Flow
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Package Aware Chip Design Value Proposition
IO, Bump, PIN placement optimization

• IC/Package Prototype and co-optimization
  exploration
• SI analysis, planning (Power planes analysis)
• Optimize IO/Bump/Pin placement
• Bump pattern/Tile Synthesis with RDL route
• Escape route for bumps with minimum package
  layers

Technology
Lower Cost
Quicker to Market
TTM

• Save weeks to months in design time
• Early exposure to entire Package/Pad/IO
• Ability to handle changes late in design cycle
• First Pass success for Chip/Package/PCB

Cost Savings

• Chip Die area reduction (10)
• Package/PCB area/layers reduction
• NRE cost of third-party (300K-500K per
  project)
• Fewer resources per chip (1 per project from 6)

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Chip/Package Convergence Toward Single Pass
Verification
Design Convergence

• Bottom-up planning w/DEF floorplan
• Major Steps
• Create power groups and voltage domains
• Map power groups/regions to new core plan
• Place final I/O cells and route RDL
• Route final package/s
• Extract/simulate I/O to ball interconnect
• Value Results
• Export chip to PR tools for extraction and
  verification
• Export package file for final routing

• Top Down Planning w/netlist
• Major Steps
• Generate I/O netlist, power groups and area
  blocks
• Split power groups and assign regions
• Synthesize I/O rings and place I/O cells
• Value Results
• I/O placement for core planning
• Detailed package routing
• Initial package design start

• Early Prototype phase
• Major Steps
• Compile I/O ring
• Explore package options
• Value Results
• Initial die size and I/O sequencing
• Package options and total packaged/chip cost
  estimate

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Unified Data Model Enables Cross Domain Synthesis

• All elements of the interconnectare captured and
  modeled
• Cross domain co-optimization
• Repository for golden interconnect between
  chipand package
• Connectivity management from start of design
  through final verification

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Technology Advances
Core Limited Die
Die/Package with planar routing
I/O Cells
Pad limited Die
Core area
I/O Cells
Open Space
Core area
Open Space

• Package optimization
• Exploration of die/package I/O plan minimizes
  layer count and enables accurate package cost
  estimates
• Package level power distribution planning
  facilitates balanced power deliver to die and
  minimizes surprises
• Concurrent design results in timely 1st package
  delivery
• Intelligent bump/ball assignment enables planer
  routes that frees space for plane stapling and
  decaps for better power distribution
  

• Die optimization
• In core limited die, greater optimization of
  I/O pad ring can increase core size
• In pad limited designs, variable pitch bump
  patterns can reduce overall die size
• Bi-directional flow supports I/O placement based
  on core or package driven constraints
• Signal/Power/Ground ratio automation
• 65/45 nm equals more pad limited designs

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Chip/Package Interconnect

• Interconnect synthesis must take entire
  interconnect into consideration to enable
  chip/package co-optimization
• Package route feasibility is key to up front
  final cost estimates
• Package tradeoffs can lead to significant cost
  reduction

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Complete Interconnect Analysis
Early driver to PCB extraction and analysis
avoids surprises at verification
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Design Initialization
Initial chip/package
CO-DESIGN FLOW
Design Initialization
Tiling
Global I/O Placement

• Full integration with
• OpenAccess enables interface to third party PR
  tools
• Die input
• LEF for standard cells and hard macros and I/Os
• DEF for netlist
• IBIS I/O driver models
• Support for existing tile libraries if
  presentbut not required
• Package input
• TechFile from package design team or
  sub- contractor
• Net constraints
• Voltage domains, differential pair and
  bus constraints

I/O Ring Synthesis
Detailed I/O Placement
Package Escape Route Ball/Pin Assignment
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Prototype Global I/O Placement
CO-DESIGN FLOW
Global I/O Placement
Design Initialization
Global I/O Placement
I/O Ring Synthesis

• Must support fixed or partially placed floorplans
• Global placement is flyline based and establishes
  first pass at I/O sequencing
• Automatic grouping and regioningof I/O
• Ever greater need for prototype flow to support
  accurate Request for Quote estimates for both die
  and package
• Manual placement capability to fine tune initial
  placement

Detailed I/O Placement
Package Escape Route Ball/Pin Assignment
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I/O Ring Synthesis
I/O Cell Floor Plan
CO-DESIGN FLOW
Design Initialization
Global I/O Placement

• I/O Planning synthesizes a set of templates and
  bump macros for each power group or area I/O
  block
• Cell instances define the I/O ring where I/O
  cells are to be placed
• Need to ensure that there are an adequate number
  of I/O sites to support the number of signals on
  the die
• Calculate the number of power/ground sites
  required to meet the signal/power/ground ratios
  (SSO)
• Need to ensure that there are an adequate amount
  of bumps to support the number of signals and
  associated power and ground
• Calculation of bump spacing must be based on
  package routing constraints and enable DRC clean
  escaping
• Full support for area I/O and SerDes blocks

I/O Ring Synthesis
Detailed I/O Placement
Package Escape Route Ball/Pin Assignment
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Detailed I/O Placement
Detailed Placed I/O
CO-DESIGN FLOW
Design Initialization
I/O Sequence w/RDL
Global I/O Placement

• Final step in I/O planning process
• Automatic placement of I/O cells establishes
  connectivity between cells and bumps
• Must honor user defined placement constraints
• Need to insert the proper number of power and
  ground cells based on established SPG ratio
  requirements
• Must assign bumps in cells as well as bump macros
  to I/O nets
• Finally, this step must perform RDL routing from
  I/O pads to bumps to establish an accurate
  interconnect

I/O Ring Synthesis
Detailed I/O Placement
Package Escape Route Ball/Pin Assignment
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Package Escape Route and Ball/Pin Assignment
Routed Package
CO-DESIGN FLOW
Design Initialization
Escape Routing
Global I/O Placement

• Automatic escape layer assignment
• Must honor techfile design rules when escaping
  die
• Must automatically escape power and ground
  netsto assigned power/ground layers on the
  package
• Escape signal nets to assigned package layers
• Route escape routes using min DRC rules
  toperimeter of the die
• Assign nets to balls to establish line of
  sight,single layer planar routing
• Must support any previously assigned balls
• Must honor net constraints such as differential
  pair when assigning balls to nets
• Route from die perimeter to balls using relaxed
  line/spacing rules

I/O Ring Synthesis
Detailed I/O Placement
Package Escape Route Ball/Pin Assignment
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Prototype Timing and SI Analysis
CO-DESIGN FLOW
Design Initialization
Embedded SI Analysis
Global I/O Placement

• RLC estimation is performed on final routed nets
• Parasitics values need to be generated for both
  primary and coupled nets
• On-chip parasitics need to be generated basedon
  the per-unit value for each layer in the
  techfile
• Package estimates can be based on empirical
  models and package vias are modeled as lumped RLC
  values
• Integrated parasitic (R,L,C, Mutual and coupling)
  extraction
• Load models and terminations can be used forthe
  PCB
• Timing analysis for delay, over/undershootand
  ringback

I/O Ring Synthesis
Detailed I/O Placement
Package Escape Route Ball/Pin Assignment
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Prototype PI Analysis
CO-DESIGN FLOW
Embedded PI Analysis
Design Initialization

• Power analysis support for time domain and
  frequency domain analysis
• For packages characterization, a field solveris
  needed to compile a set of templates based on the
  package stack-up and mesh structure
• Equation based models can be used to quickly
  estimate the capacitance effect in the package
• Voltage domains should be automatically cut and
  modeled based on electrical and physical
  constraints
• Adaptive meshes need to be generated for each
  voltage domain as described by the plane
  geometries and associated traces and shapes for
  rapid analysis
• Quick analysis capability enables exploration
• Reports and plots can be generated

Global I/O Placement
I/O Ring Synthesis
Detailed I/O Placement
Package Escape Route Ball/Pin Assignment
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Design Export
CO-DESIGN FLOW
Example of design design exported to package and
IC tools
Design Initialization
Global I/O Placement

• Final chip netlist along with associated macro
  cell libraries need to be exported with cover
  macrosand RDL to any chip tool supporting
  LEF/DEF
• DRC clean final package escape routing would
  thenbe exported directly back into package
  design tool
• Must also include bump to ball netlist
• Constraints defined in such as differential
  pairsmust also be automatically captured and
  passedalong down stream
• To support existing flows, netlist, including all
  I/O-bump-ball connectivity should be exported in
  spreadsheet format
• Final verification must be done using 3D
  analysisand final verification tools

I/O Ring Synthesis
Detailed I/O Placement
Package Escape Route Ball/Pin Assignment
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Key Value Proposition in Concurrent Design

• Lighting fast prototype capability
• More exploration/what if analysis on chip
  floorplan, package substrate and design rules
  (results in optimal die size and package)
• Reduce cost
• Saves engineering resources and results in lower
  development cost
• Smaller die size and less expensive package
• Correct by construction and co-optimization
• IO ring synthesis capability guarantees package
  routability
• One pass package design flow eliminates
  iterations and reducestime to market
• Early (prototype) signal and power integrity
  analysis (no more surprises at verification)