Title: Fully Parallel Learning Neural Network Chip for Real-time Control
1Fully Parallel Learning Neural Network Chip for
Real-time Control
- Students (Dr. Jin Liu), Borte Terlemez
- Advisor Dr. Martin Brooke
2Combustion Instability Control -Simulation
Results Review
- Simulated Neural Net and Combustion
- One-frequency Results
- Multi-frequency Results
- Parameter Variation Results
- Added Noise Results
3Simulation Setup
4One Frequency Plant without Control
5One Frequency Result
f 400Hz b ?
6Two-Frequency Results
f 400Hz 700Hz b ?
7Parameter Variation Results
f 400-600Hz z 0-0.008 b 1-100
810 Added Noise Results
f400Hz z0.005 b1
9Neural Network Chip Control of Combustion
Instability
10Experimental Setup
11Test Box
12Experimental Result
f 400Hz z 0.0 b 0.1
13More Results
f 400Hz z 0.0 b 0.1
14More Results
f 400Hz z 0.0 b 0.1
15Details of Initial Oscillation Suppression
Error Decreases
f 400Hz z 0.0 b 0.1
16Details of the Continuously Adjusting Process
Error Decreases
f 400Hz z 0.0 b 0.1
Error Increases
17Experiments with Run Time
f 400Hz z 0.0 b 0.1
18Experiments with Damping Factor z0.001
f 400Hz z 0.001 b 0.1
19Experiments with Damping Factor z0.002
f 400Hz z 0.002 b 0.1
20Summary of NN Chip Control of Simulated
Combustion Instability
- The NN chip can successfully suppress the
combustion instabilities within around 1 sec. - The NN chip continuously adjusts on-line to limit
the engine output to be within a small magnitude. - I/O card delay and engine simulation delay
- 30 times longer than real time
- Weight leakage
- Fixed learning step size
21Improved Neural Network Chip in 0.35- mm Process
- Seven Time More Neuron Cells
- Two layers
- Each layer has 30 inputs instead of 10
- Totally 720 neurons instead of 100
- Adaptive Learning Step Size
- Capacitor charge sharing scheme
- Current charging and discharging scheme
- Partitioned Error Feedback
- Synchronized Learning, without stopping the clocks
22New Chip
23Chip Architecture - Block Diagram
24Cell Schematics
Cell
Cell
25Full Chip Spice Simulation after Parasitic
Extraction
- Shift Register
- Weight Updating
- Current Outputs at Pads
- Clocking Scheme
26Shift Register
X1ms First 0 to 1 at sh_in
X15.4ms First 0 to 1 at sh_out_end 720 cycles of
delay
X1.48ms First 0 to 1 at sh_out_1r 24 cycles of
delay
27Weight Updating
Shifted in voltage
Weights
28Output Currents at Pads
29Clocking Scheme for Learning
One clocking cycle is 20 ms
30Conclusion
- Extensive software simulations to provide a
solution for real-time control using the RWC
algorithm, with direct feedback scheme - Successful application of the analog neural
network chip to control simulated dynamic,
nonlinear system - Improved chip resulted from the extensive
hardware experiments - Automated test method and system
31Future Works
- Acoustic Oscillation Suppression
- Test of the New Chip
- Real Combustion System Control
- Third Generation Chip (10,000 Weights)
32Acoustic Oscillation Setup
33The Two Layer Board