Rail to Rail Input Amplifier in '25um CMOS with High Unity Gain Frequency

1
Rail to Rail Input Amplifier in .25um CMOS with
High Unity Gain Frequency

• TEAM
• Arun Ramamurthy
• Amit M Jain
• Anuj Gupta

2
Specifications

• Gain 70dB
• Phase Margin 65
• Unity Gain Frequency 100MHz
• Capacitive Load 2pf
• Supply voltage variation /- 10
• Temperature Range 27C to 85C
• Output Swing 1V

3
Basic Circuit.

• Architecture

Input Stage
Gain Booster Stage
Summing Circuit
Output
Differential Input
4
Rail to Rail Input Stage with Gm Control

• Low Vcm PFETs amplify
• High Vcm NFET amplify
• Mid-Range Vcm Both NFETs and PFETs amplify
• Gain should remain constant throughout.
• Gm varies with sqrt of current
• Thus four times current in Low and High Vcm
• Swiches used to route
  currents.

V
5
The Summing Circuit
VDD

• The previous input stage is
• Differential input and
• Differential output stage.
• The output from this stage
• is a single output
• The currents from the input
• stages have to be added
• in this stage.

N Pair Input
-
Out
P Pair Input

-
VSS
6
Output after Summing Circuit
7
The Output Booster Stage
VDD

• Gain -Gm (r0nr0p)
• The summing circuit in previous stage does not
  provide any amplification.
• To meet specs a high gain amplifier has to be
  added.
• Many stages cannot be added due to phase and
  bandwidth deterioration
• High W/L and current helps to amplify.
• The response before this stage and the response
  after this stage.

Current Source
Vout
Vin
VSS
8
Without Capacitance and Resistance
68 dB GAIN
Unity Gain Frequency125MHz
Phase -230 !!
9
Frequency and Bandwidth Compensation
VDD
N Pair input
Out
P Pair input
VSS
10
Results
Gain, Phase Margin and Unity Gain with Miller
Capacitance Only
68 dB GAIN
Unity Gain Frequency55MHz
Phase -115 !!
11
Gain, Phase Margin and Unity Gain Frequency at
VCM 2.5 V
68 dB GAIN
Unity Gain Frequency100MHz
Phase -105
12
Schematic
13
Layout
14
RESULTS
15
THANK YOU!!

• Questions?