Alpha AXP Architecture

1
Alpha AXP Architecture

• Dr. Richard L. Sites
• Digital Technical Journal
• Volume 4, Number 4
• Special Issue 1992

Shyam Bukka Friday,
January 30, 2004
2
Dr. Richard L. Sites

• Employment
• IBM
• Hewlett-Packard
• Burroughs
• Digital Equipment Corporation (1980) significant
  contributor to the Alpha AXP architecture
• Education
• B.S. in Mathematics form MIT
• Ph.D. in Computer Science from Stanford
  University
• Post-doctoral work at the University of North
  Carolina (computer architecture)

3
ALPHA AXP DESIGN GOALS

• 1. High Performance.
• 2. Longevity.
• 3. Capability Of run both VMS and Unix
  Operating Systems.
• 4 Easy migration from VAX and MIPS
  architectures.
• PAL ( Privileged Architecture Library )code lets
  Alpha AXP
• Implementations run the full Open VMS AXP
  and DEC OSF/1 and Windows NT AXP operating
  systems.

4
PAL Code

• It is a Privileged Architecture Library (PAL
  Code)
• 1. It contains a set of Subroutines that are
  specific to a
• particular Alpha AXP Operating System
  Implementation.
• PAL Code is written in Standard Machine
  Code.
• 2. It provides the Operating System
  Primitives like Context Switching , Interrupts ,
  exceptions and Memory Management.
• 3. It is written in a standard machine code
  language and it is accessible by implementation
  hardware or CALL_PAL instructions.

5
Performance And Longevity

• Performance
• Alpha AXP architecture is listed in Guinness Book
  Of World Records as the worlds fastest
  single-chip Microprocessor.
• Longevity
• The longevity of Alpha AXP is increased by 1000
  times by the following three considerations.
• Fast Cycle Time Implementations.(10 times)
• Multiple Instruction Issue (MII).(10 times)
• Multiple Processor Implementation.(10 times)
  

6
Key Design Issues

• RISC.
• Full 64-bit design.
• Register File.
• Multiple Instruction Issue (MII).
• Shared Memory Multiprocessing.

7
Multiple Instruction Issue (MII)

• MII Starting more than one instruction at
• Once.
• No Branch Delayed Slots.
• No Suppressed Instructions.
• No Byte Load/Store Instructions and Implicit
  Unaligned accesses and no Partial Register
  Writes.
• No Arithmetic Exceptions.
• Cray-1 Model of Arithmetic Exceptions are adopted
  in first AXP architecture (Exceptions are
  reported at the end of the event).
• Explicit TRAPB ( TRAP Barrier) Instruction.

8
Branch Delayed Slots

Optimized Del. Jump
Address
Delayed Jump
Normal Jump
100 101 102 103 104 105 106
LOAD X , A ADD 1 , A JUMP 105 ADD
A , B SUB C , B STORE A , Z
LOAD X , A ADD 1 , A JUMP 105 NOP ADD
A , B SUB C , B STORE A , Z
LOAD X , A JUMP 105 ADD 1 , A ADD
A , B SUB C , B STORE A , Z
9
Example for Aligned Access
Data

• Accessing Data from 0th word
• Data(158) AB
• Data(70) FF
• Aligned Access

Memory Address
15 8 7
0
16 Bit Data Bus
10
Example for Unaligned Access
Data

• Accessing Data from 1 word
• Data(158) AB
• Data(70) 12
• Un aligned Access

Memory Address
15 8 7
0
Data Bus
11
Shared Memory Multi Processing

• Load Locked
• In-Register Modify
• Store-Conditional
• Test

12
Data Representation

• Data Characteristics
• All Operations are done between 64-bit
  Registers.
• Memory is accessed via 64-bit Virtual
  Addresses, using the little-endian or,
  optionally the big-endian byte numbering
  convention.
• There are 32 integer registers(R310) and 32
  floating-point registers (F310).
• Longword(32-bit) and Quadword (64-bit) integers
  are supported.

13
Data Types

• 1. Four Integer data types are
  supported
• Byte
• Word
• Longword
• Quadword
• 2. Five floating point data types are
  supported
• VAX Floating Point Formats
• VAX F_floating (32-bit)
• VAX G_floating(64-bit)
• IEEE Floating Point Formats
• IEEE single (32-bit)
• IEEE double (64-bit)
• IEEE extended (128-bit)

14
Integer Data Representation
1. Byte Format

• 8-bit Data item.
• It is supported by the extract, insert ,
  zap instructions.

7 0
A
2. Word Format

• 16-bit Data item.
• It is supported by the extract, mask, insert
  instructions.

15 0
A
15
3. Longword

• 32-bit Data item.
• Bit 31 is the Sign bit.
• It is supported by sign-extended load/store
  instructions and longword arithmetic instructions.

31
0
A
4. Quadword

• 64-bit Data item.
• Bit 63 is Sign bit (Signed Integer).
• It may be a Signed Integer / Un signed Integer

63 0
A
16
VAX Floating Point Formats

• 1. F_floating Format
• Memory Format

• If Exp0 and S0 Then Value 0.
• If Exp0 and S1 Then it is a Reserved
  Operand.
• Range 0.2910-38 Through 1.71038.
• Precision is 7 decimal digits.

Frac. Hi
Exp.
S
Fracton. Lo
31 16 15 14
7 6 0

• Register Format

0
S
Exp.
Fraction
63 62 52 51
29 28
0
17
IEEE Floating-Point Formats

• IEE Floating-Point Formats

Basic
Extended
Single
Double Single Double

• The values representable within a format are
  specified by using three integer parameters.
• P --- Number of fraction bits.
• Emax --- The Maximum exponent.
• Emin --- The Minimum exponent.
• Within each format following entities are
  permitted.
• Numbers of the from (-1)S x 2E x
  b(0).b(1).b(2)b(P-1)
• S0 or 1
• E any integer between Emin and Emax,
  inclusive
• b(n) 0 or 1
• Two infinities-positive and negative
• At least one Signaling NaN
• At least one Quiet NaN

18
BASIC

• Basic Floating Data type Formats
• Single

A
Exp.
S
Fraction.
Memory
31 30 23 22
0
A Register
S Exp. Fraction
0
63 62 52 51
29 28
0

• Double (T_floatong )
• Memory
• Register

31 30 20 19
0
A A4
Fraction Lo
S
Exponent
Fraction Hi
S
Exp.
Fraction
0
63 62 52 51
32 31
0
19
Instruction Formats

• Four Fundamental Instruction formats are there
  in Alpha AXP.
• Operate Instructions.
• Memory Instructions.
• Branch Instructions.
• CALL_PAL Instructions.
• All Instructions are 32-bit wide.
• They reside aligned long word addresses.
• Each Instruction contains 6-bit Opcode. And zero
  to three 5-bit Register-number fields, RA,RB,RC.
• The remaining bits contains function (opcode
  extension), Literal, or Displacement fields. RB
  is never Written and RC is never Read.

20
Operate Instructions

• Instruction Format

1
Func Func.
Integer, Litteral Integer,Register Floating Point
Literal
OP
RA
RC
0
RB
///
Func.
RB
6 5 5 11
5

• There are five groups of register-to-register
  operate instructions Integer, Arithmetic,
  logical, byte manipulation and miscellaneous
  instructions.
• All Operate Instructions are three-operand
  register- to-register instructions and operate on
  64-bit Quadwords unless otherwise specified.
• The Instruction is in the form of RCRA
  Operate RB.
• In Integer operates , the opcode and a 7-bit
  function field specify the exact operation.
• Integer operates may have an 8-bit zero-extended
  literal instead of RB.
• In floating-point operates, the opcode and an
  11-bit function specify the exact operation.
• There are no floating point literals.

21
Example for Opearte Instruction

• Longword Add
• Format
• ADDL
  Ra.rl,Rb.rl,Rc.wq !Operate Format
• ADDL Ra.rl,b.rl,Rc.wq !Operate
  Format
• Operation

SEXT((RavRbv)lt310gt)
Rc
Exceptions Integer Overflow
Instruction Mnemonics ADDL
Add Longword
Qualifiers Integer Overflow
Enable (/V)
22
Memory Instruction

Instruction Format

31 26 21 16
0
OP
RA
RB
Displacement
6 5 5
16

• Memory Format Instructions are used for loads,
  stores, and a few miscellaneous operations.
• Loads /Store are two operand Instructions,
  Specifying Register RA and a base-displacement
  virtual byte address.
• The effective address calculation sign extends
  the 16-bit displacement to 64 bits and adds the
  64-bit RB register.
• The resultant virtual byte address is mappe d to
  the physical address.
• The miscellaneous instructions makes the other
  uses of RA,RB registers.

23
Example For Memory Instruction

• Load G_floating
• Format
• LDG
  Pa.wg,disp.ab(Rb.ab) !Memory Format
• Operation
• Va
  (RbvSEXT(disp))
• Fa
  (Va)lt150gt(Va)lt3116gt
• 
  (Va)lt4732gt(Va)lt6348gt
  
  
• Exception
• Access Violation
• Fault on Read
• Alignment
• Translation Not Valid
• Instruction Mnemonic
• LDG Load
  G_floating (Load D-floating)
• Qualifiers
• None.
• 
  

24
Branch Instruction Format

• Instruction Format

31 26 21
0
OP
RA
Displacement
6 5 21

• Branch Instructions specify a single register RA
  and a signed PC-Relative longword displacement.
• The branch target calculation shifts the 21-bit
  displacement left by 2 bits to make it long word
  displacement then sign extends it and adds to the
  updated PC.
• Conditional branch instructions test register
  RA, and unconditional branches write the updated
  PC to RA for subroutine linkage.
• Calculated jump instructions write the updated
  PC to RA and then jumps to the target address in
  RB.

25


CALL_PAL Instruction

• Instruction Format

31 26
0
Function
OP
6 26

• The CALL_PAL Instructions has only a 6-bit
  opcode and a 26-bit function field.
• The function field is a small integer
  specifying one of a few dozen privileged
  architecture library routines.