Design Flows for Integrated Radios Where are we going and why

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Design Flows for Integrated RadiosWhere are we
going and why?

• Rhett Davis
• BWRC Lunch Meeting
• June 30th, 2000

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Questions for the Day

• What makes complex digital system design so
  hard?
  
• What is the world doing about it?
• What am I doing about it?
• How should we build integrated radios?

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The Slide
SpecificationMatlab, Opnet
Conceptual
Opnet, VCC
Matlab
Matlab
Behavioral
Simulink
Simulink, Stateflow
C, Stateflow
Structural
Synopsys, Cadence, Unicad
Spectre and Spectre RF
ARMulator,ARM Compiler
Physical
Agilent ADS ASITIC Cadence
ARM FPGAs
Unicad Cadence, Mentor Power TimeMill
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The Slide January 00
Specification (C, Matlab, SDL)
Behavioral
Behavioral/ Structural
VCC, Opnet, Telelogic, Stateflow
Stateflow Simulink
Matlab, Simulink
Structural
Unicad, Cadence, Synopsys
Spectre
ARMulator,ARM Compiler
Physical
HP EESoft ASITIC Cadence
ARM FPGA Express
Unicad Cadence, Power TimeMill
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The Slide August 99
Specification(UML)
Conceptual
Rational ROSE,Visual Modeler
Behavioral
Matlab, Ptolemy
Matlab, Ptolemy
Telelogic, Matlab Ptolemy
Structural
Synopsys, Unicad
HSPICE
ARMulator,ARM Compiler
Physical
HP EESoft ASITIC Cadence
ARM FPGA Express
Unicad Cadence, Power TimeMill
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The Other Slide
Flexibility
Embedded Processor
DSP (e.g. TI 320CXX)
Reconfigurable Processor (Maia)
Embedded
FPGA
Direct Mapped
Inefficiency
Hardware (MUD)
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Whats the Real Problem?
vs.
Circuit Designers
CAD Developers
CAD tools arent any more advanced today than
they were 10 years ago.
CAD tools would work very well if circuit
designers would use them properly.
Translation CAD Developers Suck
Translation Circuit Designers Suck
Can we find an answer that doesnt insult anyone?
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A Simple Design Example

• Target Clock Rate25 MHz (40 ns Period)
• Delay 30 ns
• Delay 15 ns

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Timing Constraint Violations

• Connecting blocks would violate maximum clock
  period
  
• Pipeline register alleviates problem
• Block modification required

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Loop Retiming

• When adding registers to a loop, the entire loop
  must be retimed
  
• Multiple blocks might need to be modified

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Modification Chain Reaction

• Changing one block leads to a cascade of changes
• Fundamental Problem of Register Transfer Level
  (RTL) Design Methodology

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Behavioral Synthesisan alternative to RTL design

• Designers specify scheduling constraints instead
  of cycle-to-cycle behavior
  
• Behavioral Compiler schedules and retimes
  automatically

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Efficiency of Behavioral Synthesis
Behaviorally synthesized ASICs tend to look like
specialized processors.
Behavioral Synthesis
Note from CAD Developers Behavioral Synthesis wo
uld be more efficient if circuit designers didn
t suck.
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Problems with Timing Closure
No tool has all of the timing information,
Looping between tools causes chain reaction which
never settles
Why does it take so much time to go between
levels?
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Why Designers Hate CAD Tools

• Names arent preserved between levels of
  description
  
• Different Naming Restrictions
• Illegal in EDIF
• Illegal in Cadence / \
• Used by Synopsys /
• Different Representations of Hierarchy
• Can you find the red connection in the top
  graph?
  

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Time-to-Market Constraints
First to market wins. Second breaks even. All
others lose.
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A Typical Chip Architecture Meeting

• We could try X
• That will never work. I have a friend who tried
  X, and it never worked for him
  
• But I have a friend who says it works great!
• Yeah, but s/he was trying to make Y! X works
  great on Y!
  
• What do you think we should try?
• I think we should go with Z.
• Oh, no you dont... we learned 10 years ago that
  Z is a waste of time.
  
• What else is there?
• (pause)
• We could try X
• ...

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What Can We Do?

• Consolidate all timing information in one view
• Speed up the chain reaction (deep automation)
• Search for architectures which are efficient but
  avoid the timing closure problem

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Unified Description
Names match!
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SSHAFT API for Deep Automation
An Automated Design Flow is a directed, acyclic
dependecny graph
step

• SSHAFT API Provides a mechanism for
• Dependency Checking
• Error Trapping
• Evaluation of Execution Time
• Maintenance of this API allows us to explore
  architecural choices, rather than making
  unqualified guesses

dependency
target
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Comparison of Complex MACs
Custom Module
ICMake Composite
Hand - authored Std. Cell Netlist
Synthesized Std. Cell Netlist
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Summary
Thanks for listening!