ANNEX D Development of a Risk Informed Avionics Technology Insertion Roadmap

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ANNEX DDevelopment of a Risk Informed Avionics
Technology Insertion Roadmap
Chris Wilkinson Senior Research Scientist CALCE
Electronic Products Systems Center University
of Maryland chrisw_at_wam.umd.edu,
http//www.calce.umd.edu

• Project Objectives
• To develop a risk-informed avionics technology
  roadmap and to define the impacts of new
  technology insertion and old technology
  dependence on avionics
• To develop recommendations for avionics design
  and support practice

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CALCE Center Programs
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CALCE Center Sponsors (2000)

• 3Com
• ABB
• U.S. Air Force
• ATOTECH
• Avici Systems
• BG
• Boeing
• BAE Systems
• Celestica
• Ciena
• CNES
• Rockwell Collins
• Corvis
• CSP, Inc.
• Daewoo Electronics
• DaimlerChrysler
• Delphi Delco
• DERA (U.K.)
• EADS (Aerospatiale) Matra

Eldec Corporation Emerson Ericsson Radio Systems
AB GD Information Systems General
Motors Hewlett-Packard Honeywell Indium Solder
Intel InterCon International Rectifier Israeli
MoD Johnson Matthey Kings Electronic
Components Lab. of Physical Science Lockheed
Martin Lucent Technologies MacDermid Matra BAe MD
Robotics Microsoft Motorola
MTI NASA Goddard Space Center NASA Jet Propulsion
Lab Naval Surface Warfare Center Nan Ya
Plastics Neocera Nokia Radio Systems Nortel
Networks Northrop Grumman NSA Office of Naval
Research Orbital Sciences General
Motors Philips Photocircuits Price Systems
L.L.C. QualMark Raytheon Systems Company
RD Instruments Rocketdyne Sandia National
Labs Schlumberger S. C. Johnson Seagate LeCroy Smi
ths Industries Sonix Sun Microsystems Tatung Tera
dyne Textron Systems Thomson Consumer
Electronics Triquint TRW Lucas Aerospace United
Technologies UK MoD U.S. Army AMSAA U.S. Air
Force WPAFB Visteon Automotive Systems Wilcoxon
Research
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Key Problems Facing Avionics

• Responding to the loss of the traditional supply
  chain
• Managing Obsolescence
• In manufacturing, maintenance
• Continuous new technology insertion
• Reducing sustainment costs of
• Design re-design
• Maintenance support
• Certification re-certification
• Lower part temperature range capability
• Supporting legacy systems

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Why an Avionics Roadmap?

• The continued decline in military grade parts is
  forcing avionics suppliers to switch to
  commercial part/sub-system technology.
• Brings problems of reduced temperature range,
  rapid obsolescence, high IO SMD packaging.
• Requires consequential changes to
• Parts selection process
• Aircraft cooling provisions
• Certification process
• Hardware design process
• Roadmap is collecting data on the changes
  occurring in the component marketplace and
  recommending the changes to the above processes
  which are needed.

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World Semiconductor Market
Source INSTAT March 1999
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Decreasing Military Parts Availability
Total U.S. military/aerospace microcircuitavailab
ility of parts
Includes QMLs, QPLs, 883 devices Standardized
parts include package variation, functionality,
lead finish, quality variations and qualified
manufacturers Source Baca, M., "Obsolescence
Management in the Twenty-first Century", DMSMS
Conference, San Antonio, Texas 1997
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Manufacturers Exiting the Military Market
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Manufacturers Exiting the Military Market
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Part Functionality

• The number of transistors/cm2 will continue to
  follow Moores Law for the foreseeable future
• Equates to ?P throughput, memory density, ASIC
  gate count, etc
• Projections for lithography suggest this will
  happen
• Gate delays will continue to fall, enabled by
  factors such as low-K dielectric and copper
  interconnects

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Military Temperature Range

• All avionics design will be based on parts with a
  recommended operating range of 0-70oC or less
  within 5 years.
• Military part suppliers are exiting the market.
  Of the few that are left, we do not expect any
  significant players to continue military part
  production beyond the next 5 years.
• Industrial and automotive parts do not cover the
  variety needed by avionics

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Part Supply Voltage

• Supply voltage will continue to reduce
• 5v will largely be gone in 2 years
• Lower voltage trend is driven by the need
• for chips with smaller feature sizes
• More dies per wafer lower cost/die
• Higher speed/density increased functionality
• to maintain field strengths at or about the
  current level and not increase failure rate due
  to mechanisms such as
• gate oxide breakdown
• hot carriers
• Low-K dielectrics will alter this trade-off

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Design Trends in Memory Devices
Adapted from The SIA Roadmap, 1999 and Prince,
B., High performance memories, 1999.
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Low-k Dielectric Materials

• Major advantages of low-k (klt3.0) dielectrics
  are
• Lower device capacitance
• Lower signal propagation delay
• Lower noise
• Reduces power dissipation 1.
• Some of the issues with low-k dielectrics are
• development and integration of low-k materials
• extensive material characterization
• electrical performance in the materials, which
  are generally accepted to be necessary to
  continue shrinking devices while boosting their
  speed and performance 2.

Source 1 Semiconductor International, pp. 64,
September 1998 2 Semiconductor Business News,
http//www.semibiznews.com/story/OEG20000310S0050,
March 10, 2000
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Copper Interconnects

• Higher conductivity relative to Al
• Decrease in
• Signal rise time,
• power consumption,
• number of metal layers a device requires
• Cu surpasses Al in electromigration performance
• Distributed over line length rather than bunched
  as in Al

Source Design News, pp. 3-80, June 7, 1999
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Part Packaging

• Through hole packages in all sizes will continue
  to decline in favor of SMD.
• Through hole now lt 7 and falling
• BGA/CSP/FC1 will be the dominant package for high
  I/O applications.
• High I/O SM packages have severe assembly and
  solder joint reliability difficulties. Some
  commercial users have resorted to sockets
• CSP pad density requires redistribution layers
  for routeability
• Ceramic will continue to decline in favor of
  plastic in all package styles.

1BGA Ball Grid Array, CSP- Chip Scale Package,
FC Flip Chip
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Chip-scale Packages

• The extreme downsizing of electronic products
  needed to make much of todays portable computer
  and telecom gear possible, is driving chip-scale
  packages (CSPs), bare die and other advanced
  technologies
• Portable and wireless products are driving
  miniaturization, as is the need for performance.
  This increases the application of CSPs
• Today, most cellular phones have two chip-scale
  packages, an Intel flash and a Samsung DRAM in CSP

Source Electronic News, pp. 28, June 28, 1999
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Flip Chip Packages

• Flip chip packaging technology is of two types
• Flip chip on board (FCOB) The flip chip device
  is mounted directly on a motherboard.
• Applications include automotive electronics, disk
  drives, driver ICs for flat panel displays,
  watches, pagers, cellular phones, smart cards, PC
  card, and medical applications
• Flip chip in a package (FCIP) The flip chip is
  mounted in a package, such as ceramic ball grid
  array (CBGA), ceramic column grid array (CCGA),
  ceramic land grid array (CLGA), plastic ball grid
  array (PBGA) or chip scale package (CSP).
• Applications of single-chip package include
  camcorders, microprocessors, SRAMs, card PCs,
  digital video disks, and ASICs for PCs and LAN
  switches
• Applications of multichip module include
  mainframe computers, servers, workstations,
  notebooks, subnotebooks, PDAs, and transmission
  switches

Source ISHM-Nordic 1997
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Part Design Wearout Life

• Some evidence suggests that design wearout life
  may be decreasing
• Wearout factors are becoming design goals for
  major semiconductor manufacturers
• Motorola has informed Honeywell that the design
  wearout criteria for the PowerPC family is 5-7
  years, 50 duty cycle1
• Intel has stated in a JEDEC meeting that the
  Intel design wearout criteria is 7 years, 50
  duty cycle, 1 failure rate at 7 year point1
• Nullifies constant failure rate assumption of
• System safety assessment
• Logistics
• Life/Last time buys

1John Fink, Honeywell, Avionics Roadmap
Conference, University of Maryland, August 2000
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Part Uprating

• Margin for uprateability could reduce in the long
  term
• Cost penalties from wider than needed temperature
  range will be driven out
• Higher level assembly parameter conformance
  uprating methods, may be an option for ?3-5 years
• Due to reducing margin between recommended
  operating temperature specification and actual
  part capability
• Parameter re-characterization uprating may be an
  option for 5-7 years with decreasing potential
• Reducing internal margins leading to loss of
  function
• Uprating will be a solution mainly for CMOS
  digital, and a limited amount of analog and mixed
  signal parts

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The Avionics Design Process

• The Changing Environment
• The Hardware Life Cycle

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The Operating Environment

• The civil avionics business is highly regulated
• Military is largely unregulated
• Strict regulatory requirements govern
• Hardware, software, systems development
• Manufacturing and support operations
• There is now a new operating environment
• Vanishing mil-specs parts
• Decreasing part temperature range
• Decreasing part market life
• BUT - the regulations and the physical
  environment remain the same

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Things must change

• The end of the project is when a certificate is
  issued or
• when the military customer accepts the product
• Do it once and forget it
• Avionics companies complete the development cycle
  and put equipment into service
• Support of the design is minimal
• Limited to fixing broken boxes
• Continuing product development
• Short life parts mean product development will
  continue for the life of the product
• Performance upgrades will piggy-back on these
  enforced changes

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Adopt Rapid Product Development

• Traditional COTS
• Standard modules
• Standardized interfaces
• Carries excess baggage
• Loss of control
• RECOMMENDATION
• Rapid Customization
• Library of IP
• Rapid Prototyping Toolset
• Standardized interfaces
• Same for software

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Reuse Software Design

• Software is the driver
• 80 of large microprocessor based system
  development cost is software
• Of the 80 at least 50 is VV
• RECOMMENDATION
• Use in-company open architecture
• Non-proprietary software interfaces are NOT a
  requirement but have some advantages
• Use HW/SW Co-design tools
• Enables re-useable code

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Reuse Hardware Design

• The PC model will never happen
• Frequency of new major platforms is too long
• The volume is too small
• Only a few large companies have the integration
  skills
• RECOMMENDATION
• Use in-company open architecture
• Non-proprietary software interfaces are NOT a
  requirement but have some advantages
• Enables evolutionary products
• Planned technology insertion obsolescence
  renewal

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Parts Selection and Management

• PROPOSITION
• All parts will be 0-70oC in 5 years
• Commercial parts may be uprateable for no more
  than a few years
• Gives lower parts cost
• Needs better thermal management, cocooning,
  restricted operating procedures
• PSM brings additional up front costs
• RECOMMENDATION
• Use a Parts Selection and Management Process
• Think in terms of 0-70oC parts from now on

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Manufacturing

• Small fine pitch parts are easily damaged during
  manual assembly
• Latent and patent ESD
• Poor control of soldering process
• Consider utilizing EMS
• New business model, key competencies
• RECOMMENDATION
• Improve yield, lower test/rework/errors/scrap
  costs thru
• Factory automation, lessons learned loop
• Seamless integration of CAD/Materials/FMS/Tech
  Pubs Tools, Internet

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Maintenance Support

• End user 3rd level repair requires large
  investment by both end user and supplier
• Increasingly impractical
• Improved, comprehensive warranties are being
  demanded
• Power-by-the-hour
• Added importance of design for FFOP
• Rate of obsolescence is accelerating
• RECOMMENDATION
• Support by function not by part
• Eliminate level 3 maintenance, return to OEM
• Eliminate level 3 end-user documentation, depot
  repair test equipment fixturing, test software
• Obsolescence renewal through FFF module exchange

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Incremental Certification

• RECOMMENDATION Initial certification of basic
• PLUS minimal certification of additions and
  changes
• Demonstrable, robust software partitioning
• Decoupled hardware software
• Enables quick re-certification after SRM change
  or addition of new function

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Conclusion

• A structured, layered design enables products to
  be partitioned into independent pieces of IP
• Re-usable across a range of products with minimal
  change
• Refreshed independently to solve obsolescence or
  performance issues
• Defined interfaces provide change containment
  boundaries
• The certification process has to modernize to
  recognize the continuous development cycle
• Joint industry/FAA activity can make this happen
• Support will be at functional level and not at
  part level