Designing SingleChip Radios

1
Designing Single-Chip Radios

• The State-of-the-Art at BWRC

2
BWRC Statement of Purpose
Provide an environment for research into the
design issues necessary to support next
generation wireless communication systems.The
focus will be on highly integrated CMOS
implementations which have the lowest possible
energy consumption while using advanced
communication algorithms. The evaluation of these
components will be made in a realistic test
environment.
3
The Radio-on-a-Chip Design Problem

• Multiple levels of design optimization
• The fractal nature of design
• Capturing the functionality
• Capturing the architectural choices
• Quantifying the exploration trade-offs

4
The Automated Design Environment
Specification (C, Matlab, SDL)
Analog Data Processing
Protocols Control
Behavioral
Digital Data Processing
Behavioral/ Structural
VCC, Opnet, Telelogic, Stateflow
Stateflow Simulink
Matlab, Simulink
Structural
Unicad, Cadence, Synopsys
Spectre
ARMulator,ARM Compiler
Physical
HP EESoft ASITIC Cadence
ARM FPGA Express
Unicad Cadence, Power TimeMill
5
System Optimization Hierarchy
Network Level
Constraints
Constraints
Module Level
6
Digital Intercom A (Single-Chip) Radio Design
Exercise
Basestation

• Known and tested specification of limited
  complexity allows focus on architectural
  implementation methodology
• Implementation on off-the-shelf hardware available

Mobiles
Up to 20 users per cell _at_ 64 kbit/sec per
link TDMA selected as MAC protocol
7
The Intercom Protocol

• 1.6 Mbs Frequency-hopping Proxim Radio
• TDMA selected as multi-user access protocol
• Basestation manages transport layer performs
  login, creates and eliminates connections, and
  manages slot database

N Data slots
Control Up
Control Down
Contention Based
Broadcast
1 transmit slot per sender
Frame
8
The Intercom Protocol
9
Intercom I An Off-the-Shelf Implementation
10
A First-Order Prototype

• Initial implementation based on Infopad chassis
  and off-the-shelf hardware
• Software support includes RTOS and wireless
  protocol stack

11
The Intercom Design
Cable/Strap
StrongArm/ Xilinx/ Memory Board
RangeLAN II Proxim Radio
Push to Talk
Hand Held Device
Mode Switches
Power - I/O Board
Speaker
Speaker
On/Off Switch
Volume
Microphone
4 AA Batteries
12

Intercom Case Exploded Earpiece

• The earpiece houses the radio boards and
  speakers, as well as mount the microphone boom.

13

Intercom Case Exploded Handpiece

• The handpiece houses 4 buttons for setting the
  radio channels, an on/off button, volume control,
  push-to talk button, 4 AA batteries.

14

Intercom Case Assembled
15
Eventually transformed into PicoRadio Testbed

• Flexible platform for experimentation on
  networking and protocol strategies
• Modular design of stackable units
• Size 3x4x2
• Power dissipation lt 1 W (peak)

16
Protocol Definition/SpecificationFirst Generation
UML Spec

• Initial specification in UML with manual mapping
  into SDL
• SDL has asynchronous FSMs with instantaneous
  message transfer
• Functional verification through simulation
• Automatic Translation of SDL in C-code for
  Software Implementation
• Manual mapping of asynchronous FSMs into
  synchronous VHDL code and schematics for FPGA

Manual
SDL Spec
Manual
Automatic
C-Code
VHDL Schematics
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System Conception in UML
Example Digital Intercom System
Sequence Diagrams
Use Cases
Class Definitions
18
Protocol Specification in SDL
154 pages of SDL schematics and code
19
Protocol Mapping
20
Software Support Environment

• Design environment
• Compose, compile, and debug ARM applications
• Build ARM executable for embedded operation
• Design, simulate, and synthesize configurable
  logic for Xilinx
• Library of system code and radio support modules
• Operating system and device drivers
• Virtual channel abstraction
• User Application Programming Interfaces (APIs)
• Read/write API into Xilinx concept of ports
• Interrupt support for Xilinx --gt ARM
  asynchronous events

21
ARM Code Development
Debugger
Design Manager
Generates ARM executable on PC. For debugging,
executable is downloaded to ARM via serial port.
For embedded operation, executable is resident
in PROM
22
FPGA Compilation Flow
Hand Written VHDL Generate Xilinx Netlist
Format
SCHEMATIC check and create wirelist generate
EDIF
ViewLogic Tools
FPGA Express
build Xilinx-specific database (NGD) map to
FPGA technology place and route generate
generic bit file generate PROM image
Back-Annotated Simulation
generate annotated NGD generate EDIF generate
wirelists generate simulation file
Xilinx Tools
generate programmer-specific format create C
header
Our Custom Tools
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Description Complexity

• Intercom protocol on Off-the-Shelf Platform
• Protocol Spec (processor) 15,000 lines of C-code
• RTOS 13,000 lines of C-code (Angel RTOS)
• FPGA Fully Occupied Xilinx 4013 (described in
  VHDL schematics)

24
The Integrated Intercom

• Effort started September 1999
• Front-end adapted from 1.6 Mbit/sec CDMA radio
  and baseband processor already under development
  in RF and Communications groups
• Attempts to use complete design flow as advocated
  in the center
• Three identiable modules
• RF front-end A/D and D/A
• Digital baseband processor
• Protocol processor

25
The Integrated Intercom
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Goals of This Session

• For each of the three modules, discuss
• Methodology
• Specification
• Design library
• Status
• Identified problems, especially with respect to
  interfacing with other modules
• Solicit feedback and inputs