Slides for Richard FCRP Review, Washington DC

1
Calibrating Achievable Design Roundtable
Discussion June 9, 2002
Wayne Dai, Andrew Kahng, Tsu-Jae King, Wojciech
Maly, Igor Markov, Herman Schmit, Dennis Sylvester
Facilitator Bill Joyner, IBM/SRC
2
Recent Progress in Technology Extrapolation and
GTX

• Transition-aware and active-shielding global
  signaling approaches, RLC interconnect
  performance models
• Taxonomy and correlated models of process
  variability, and framework for examining impact
  on achievable design
• New DRAM access time model in support of eDRAM
  vs. multi-die cost/performance model
• Release of ITRS-2001 ORTCs in GTX
• Updated GTX version in Sematech ITRS-2001 website
• Enhancements in June02 release
• Ongoing studies, modeling of ITRS shared red
  bricks
• Low-k benefit, variability tolerance of design,
  design-limiting process rules,

3
Recent Progress in CAD-IP Reuse

• Prototype release of Bookshelf.exe
• New infrastructure that hosts executable
  Bookshelf content and allows remote execution
• Web interface, distributed computation platform,
  and scripting capabilities
• New tilable (i.e., scalable) circuit benchmarks
• Network tile
• Processing elements (floating-point adder,
  floating-point multiplier, programmable FIR
  filter)
• Initial discussions of OpenAccess API and data
  model
• Benchmark scaling approaches

4
Recent Progress in METRICS

• Expanded METRICS system to front-end acceptance
  and clock tree synthesis domains
• Work with STRJ-WG1 (Japan Roadmap group) to
  obtain design quality / value survey questions
  that will be used to survey U.S. companies
• Started to propagate open-source METRICS system
  available to university user group communities
• Exploring potential links to Bookshelf.exe
• METRICS Birds-of-Feather meeting at DAC-2002
• Developing and applying machine learning
  techniques to improve existing data mining and
  regression infrastructure

5
Summary Roles of the C.A.D. Theme

• Identify best opportunities for sharing of red
  bricks between EDA and other semiconductor
  supplier industries
• GTX studies Manufacturing Calibration Is
  low-k worth the development cost? What is the
  best interconnect process architecture for 65nm?
  What FEOL and BEOL variabilities can designers
  tolerate? What is the most cost-effective
  memory-logic integration?

C.A.D. Theme
Semi Industry

• Repository of best known methods, models, metrics
• Connects applications and drivers (e.g., ITRS
  MPU, SOC) to technology roadmap
• Connects algorithm (e.g., Fabrics) and design
  technology (e.g., Power-Energy) within GSRC and
  to designs, interconnects, devices, and materials
  ( other FRCs)
• Agent of culture change
• Measurement characterization of EDA
• Open-source CAD-IP vertical benchmarking
• New vectors e.g., reusable curriculum IP for
  VLSI, VLSI design, VLSI design technology
  education

ITRS
Living ITRS
Models and Calibrations
Design Houses
What is the design problem?
How should Design help solve ITRS red bricks?
VLSI Design Education
Manufacturing Calibration
Open-Source CAD-IP
Other FRCs
METRICS Design Process Opt
Other GSRC Themes
EDA Industry Academia
6
C.A.D. Theme Draft Roadmap
Interactions
o NEMI, C2S2 FRC app roadmaps
o Fabrics Theme Bookshelf, flows research
o Fabrics SIP design tech backplane
o ITRS community
o Power-Energy Theme capture/guide
o MSD FRC mfg calibration, manufacturability
shared red bricks
o Self-Test Theme capture/guide
o Interconnect FRC model/calib, mfg/var shared
red bricks
o NSF (education)
1/01
Today
1/99
1/04
1/05
1/03
1/01
Today
1/99
1/03
1/04
1/05
o Natl VLSI design curriculum initiative
Initiatives and Milestones
o ITRS shared red brick modeling, analysis,
roadmapping
o Vertical benchmarks cell libraries, DSP, netwk
o 30 of ITRS in GTX
o Bookshelf _at_ 25 slots, first papers
o METRICS ? broader academic release
o GTX model dirs mfg cost/cal, global sig,
mem-logic, app domains
o SIP design tech backplane is METRICized
o METRICS v.1 start industry integration
o BX.exe v.1
o GTX v.1 ITRS support
o GTX v.2 (with ITRS-2001)
o BK 25 PD adopt, 50 slot interop
o Fabrics ? C.A.D. Constructive Fabrics Themes
o Open-source RTL-GDSII flow
o Start Fabrics Thrust, initial data model / flow
discussions
7
Foci of Industry Feedback and Interaction

• OpenAccess (common data model) what is GSRC
  doing?
• CAD-IP reuse Bookshelf Slots, codes,
  functionality
• Benchmarks industry-strength validation of
  research
• Education initiative?
• National-scale VLSI education infrastructure
• ITRS needs ( how to best share red bricks)
• Incremental benefits of lower k
• Optimal interconnect stack? (balancing power
  delivery, routing density, delay and signal
  integrity performance, )
• What variability can designers tolerate?
• ESD protection impact on off-chip signaling
  bandwidth
• Understanding how ground rules impact layout
  density
• What else?

8
Roundtable Discussion Questions

• For our industrial partners in your designs,
  what is the largest problem that you face ?
• And how does the research work in this Theme
  help?
• What is being done well in this Theme?
• What could be improved?
• On one or two slides (max), each industrial
  co-facilitator please summarize key conclusions
  from this discussion.Questions and issues for
  discussion not restricted to this
  set.