Brief Introduction to Verilog

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Brief Introduction to Verilog

• Weiping Shi

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What is Verilog?

• It is a hardware description language
• Originally designed to model and verify a design
• Later became an efficient design entry method
• Allows designers to quickly create and debug
  large scale designs
• Similar to C in syntax
• Verilog will be used in later labs

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Sample Half Adder

• module Add_half (sum, c_out, a, b)
• input a, b
• output sum, c_out
• wire c_out_bar
• xor (sum, a, b)
• nand (c_out_bar, a, b)
• not (c_out, c_out_bar)
• endmodule

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Module Hierarchy

• Modules can be instantiated within other modules
• Allows for simplicity and regularity in the
  design
• Example Use two half adders to create a full
  adder

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Module Hierarchy Example

• module Add_half ( sum, c_out, a, b )
• input a, b
• output sum, c_out
• wire c_out_bar
• xor (sum, a, b)
• nand (c_out_bar, a, b)
• not (c_out, c_out_bar)
• endmodule
• Module Add_full ( sum, c_out, a, b, c_in ) //
  parent module
• input a, b, c_in
• output c_out, sum
• wire w1, w2, w3
• Add_half M1 ( w1, w2, a, b )
• Add_half M2 ( sum, w3, w1, c_in ) // child
  module
• or ( c_out, w2, w3 ) // primitive
  instantiation
• endmodule

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Alternative Half Adders

• module Add_half ( sum, c_out, a, b )
• input a, b
• output sum, c_out
• assign c_out, sum a b // Continuous
  assignment
• endmodule
• module Add_half (sum, c_out, a, b )
• input a, b
• output sum, c_out
• reg sum, c_out
• always _at_ ( a or b) // behavior description
• begin
• sum a b
• c_out a b
• end
• endmodule

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Structural v.s. Behavioral

• Verilog can be structural or behavioral
• Structural definition specifies the gates and
  their connections explicitly
• Behavioral definition specifies the functionality
  of a design
• Does not contain any structural information such
  as transistors or gates
• Logic synthesis software implements the structural

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Behavioral Example2 Bit Comparator

• module comparator (a_greater, b_greater, equal,
  a, b)
• input a, b
• output a_greater, b_greater, equal
• reg a_greater, b_greater, equal
• always _at_(a or b) // either a or b changes
• begin
• if (a gt b)
• begin
• a_greater 1
• b_greater 0
• equal 0
• end
• if (altb)
• begin
• a_greater 0
• b_greater 1
• equal 0
• end
• if (ab)

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Alternate comparator

• module comparator (a_greater, b_greater, equal,
  a, b)
• input a, b
• output a_greater, b_greater, equal
• assign a_greater (a gt b) ? 1 0
• assign b_greater (a lt b) ? 1 0
• assign equal (ab) ? 1 0
• endmodule
• Uses a conditional continuous assignment to set
  the outputs.

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Clarification

• Registers are used when an output is updated on
  an event. The value must be held until a new
  event updates that value.
• Assign statements are used when the output is
  continuously being assigned.

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Testbench

• Manipulate the module inputs to observe the
  circuit reaction
• Uses module hierarchy
• Introduces the concept of delay

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Sample Testbench for a Half Adder

• module tbench
• reg a,b // regs connect to module inputs
• wire sum,cout // wires connect to module
  outputs
• half_adder M1(cout,sum,a,b) // instantiate the
  half adder
• initial
• begin
• a 0, b 0 //time 0
• 5 a 1, b 0 //time 5
• 3 a 1, b 1 //time 8
• 4 a 0, b 1 //time 12
• 52 a 0, b 0 //time 64
• 70 finish //stops the simulation
• end
• initial
• begin
• monitor(time,a b, bb coutb
  sumb,a,b,cout,sum)//displays the variable
  values at each
• //unit of time that an event occurs

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Testbench Results

• Compiling source file "ha.v"
• Compiling source file "tbench.v"
• Highest level modules
• tbench
• 0a 0, b0 cout0 sum0
• 5a 1, b0 cout0 sum1
• 8a 1, b1 cout1 sum0
• 12a 0, b1 cout0 sum1
• 64a 0, b0 cout0 sum0
• "tbench.v" finish at simulation time 134

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FSM Example Car
accelerator
brake
speed
clock
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Behavioral Description

• module car(speed, a, b, clock)
• input a, b, clock
• output 10 speed
• reg 10 speed
• parameter stopped 2b00
• parameter fast 2b11
• always _at_(posedge clock or b)
• begin
• if (b 1 speed ! stopped)
• speed speed 1
• else if (b 0 a 1 speed ! fast)
• speed speed 1
• end
• endmodule

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Where to Get Verilog

• CD in the back of the book, if you have Verilog
  version
• Icarus Verilog
• http//www.icarus.com/eda/verilog/