332:578 Deep Submicron VLSI Design Lecture 9 VLSI Economics

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332578 Deep SubmicronVLSI DesignLecture 9
VLSI Economics

• David Harris
• Harvey Mudd College
• Spring 2005

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Outline

• VLSI Economics
• Summary

Material from CMOS VLSI Design, by Weste and
Harris, Addison-Wesley, 2005
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Implementation Choices
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VLSI Economics

• Selling price Stotal
• Stotal Ctotal / (1-m)
• m profit margin
• Ctotal total cost
• Nonrecurring engineering cost (NRE)
• Recurring cost
• Fixed cost
• Select m to ensure profit after overhead

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Non-Recuring Eng. (NRE)

• Engineering cost Etotal
• Depends on size of design team
• Include benefits, training, computers
• CAD tools
• Digital front end 10K
• Analog front end 100K
• Digital back end 1M
• Prototype manufacturing Ptotal
• Mask costs 500k 1M in 130 nm process
• Test fixture and package tooling
• Total cost Ftotal Etotal Ptotal

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Engineering Costs

• Personnel costs
• Architectural design
• Logic capture
• Simulation
• Layout
• Timing verification
• DRC and tapeout
• Test generation

• Support costs
• Computers
• CAD software
• Education/re-education

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2004 Cost Figures

• Salary 50-100K
• Overhead 10-430K
• Computer 10K
• CAD Tools (digital front end) 10K
• CAD Tools (analog) 100K
• CAD Tools (digital back end) 1M
• Share cost of back end tools over entire group
• Reduce costs by
• Module reuse
• Buying in modules from IP vendor

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Prototype Manufacturing Costs

• Include
• Mask cost
• Depends on process steps
• 500 to 30,000 for one mask
• For 130 nm CMOS -- 500K to 1M
• Test fixture costs
• PWB assembly to probe die and interface to tester
• 1000 to 50,000
• Package tooling
• Use Multi-Project Chip to save on mask costs

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Total IC Fabrication Cost

• Rpackage package cost
• Rtest test cost
• Proportional to test vectors and time to test
• W wafer cost (500 - 3000)
• N gross die per wafer
• Yw die yield per wafer (expect 70 to 90)
• Ypa packaging yield (expect 95 to 99)

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Recurring Costs

• Fabrication
• Wafer cost / (Dice per wafer Yield)
• Wafer cost 500 - 3000
• Dice per wafer
• Yield Y e-AD
• For small A, Y ? 1, cost proportional to area
• For large A, Y ? 0, cost increases exponentially
• Packaging
• Test

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Fixed Costs

• Data sheets and application notes
• Marketing and advertising
• Yield analysis

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Example

• You want to start a company to build a wireless
  communications chip. How much venture capital
  must you raise?
• Because you are smarter than everyone else, you
  can get away with a small team in just two years
• Seven digital designers
• Three analog designers
• Five support personnel

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Solution

• Digital designers
• salary
• overhead
• computer
• CAD tools
• Total
• Analog designers
• salary
• overhead
• computer
• CAD tools
• Total

• Support staff
• salary
• overhead
• computer
• Total
• Fabrication
• Back-end tools
• Masks
• Total
• Summary

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Solution

• Digital designers
• 70k salary
• 30k overhead
• 10k computer
• 10k CAD tools
• Total 120k 7 840k
• Analog designers
• 100k salary
• 30k overhead
• 10k computer
• 100k CAD tools
• Total 240k 3 720k

• Support staff
• 45k salary
• 20k overhead
• 5k computer
• Total 70k 5 350k
• Fabrication
• Back-end tools 1M
• Masks 1M
• Total 2M / year
• Summary
• 2 years _at_ 3.91M / year
• 8M design prototype

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Cost Breakdown

• New chip design is fairly capital-intensive
• Maybe you can do it for less?

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Gantt Chart for Chip Design
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Schedules

• 18-24 months for completely new chip
• lt 6 months for respins of existing chips

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Design Reuse

• Migrate design to new process
• Acquire/build new standard cell library
• Retarget the HDL description to new library
• Intellectual Property Cores
• Hard actual layout defined at mask level
• Firm actual logic-level/register netlist
• Soft described at RTL level in HDL (hardware
  description language)
• To be useful, cores must come with built-in
  self-test, test pattern delivery method, or
  external test patterns

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Summary

• VLSI Economics