LECTURE 9 DIGITAL ELECTRONICS

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LECTURE 9 DIGITAL ELECTRONICS
Dr Richard ReillyDept. of Electronic
Electrical EngineeringRoom 153, Engineering
Building
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SILICON AREA

• For any given process, cost of IC is proportional
  to chip area
• Þ designers attempt to minimise area occupied by
  each circuit element
•  
• MOS transistors achieve minimum size
• when channel dimension W and L are as small as
  can be achieved within the particular technology
• The smallest values of W and L are similar as
  they are both determined by similar
  pattern-definition processes.
• ? the ratio should not depart greatly from
  unity
• unless need to drive high-capacitance or low
  resistance loads.

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Power Consumption

• Power Consumption should be minimised in the
  design of ICs.
• Depending on pin-count and construction DIL IC
  packages can dissipate 0.5 2W without excessive
  temperature rise above normal ambient room
  temperature
•  
• Since 10,000 or more gates can easily be
  accommodated on one LSI circuit chip
• Average power consumption per gate in LSI
  components should be in the range of 100?W or
  less
• battery operated digital systems should consume
  less !!

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MOS Inverters

• Digital MOS circuits can be classified into two
  categories

• Classification depends on whether periodic clock
  signals are necessary to achieve combinational
  logic functions.

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Static and Dynamic

• Static circuits
• require no clock or other periodic signals for
  operation in combinational logic networks
•  
•  
• Dynamic circuits
• require a periodic clock signals synchronised
  with data signals for proper operation even in
  combinational logic applications.
• Clock signals are applied to load elements and
  transmission gates or transfer gates and not to
  normal logic gate inputs

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Basic Inverter

• The inverter is the basic circuit with which most
  MOS logic circuits are developed.
• DC and Transient analysis together with design
  techniques developed for the inverter can easily
  be extended to NOR and NAND gates.
•  
• Analysis methods and techniques are important as
  alternative load elements are used.
• Resistor Load
• Saturated Enhancement Mode Loads
• Linear Enhancement Mode Loads
• Depletion Mode Loads

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Basic Inverter

• These load elements can be compared on the
  following Inverter Analysis basis
• DC Voltage Transfer Characteristics
• Noise Margins
• Propagation Delay
• Power Dissipation
• Circuit Density

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Basic Inverter

• The basic NMOS inverter circuit

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Basic Inverter

• In contrast to bipolar technology such as TTL,
  linear resistors are rarely used as the pull-up
  element in an inverter.
• Depletion mode devices are used as pull-ups
• Used to simplify the fabrication process
•  
• To provide greater current when the pull-down
  devices is first turned off and a capacitive load
  must be charged.

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Static NMOS Inverter Analysis

• Consider a single NMOS transistor connected with
  a resistor load to form an inverter.

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Static NMOS Inverter Analysis

• Nominal Logic 0 and Logic 1 voltage values should
  fall within specific ranges
• Thus small variations in logic input voltages
  have little or no effect on output voltage
•  
• The desired results can be achieved at the low
  input level if the input voltage remains below
  the transistor threshold voltage VT.
• i.e. if ?
• ?

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Voltage Transfer Characteristic

• The resistor current is equal to the NMOS drain
  current
• can be expressed as a function of VDS.
•  
• This is a linear relationship between ID and VDS
  for a constant RL.

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Voltage Transfer Characteristic

• This suggests that the voltage transfer function
  characteristic can be obtained graphically
• HOW ?
• by superimposing the output load (resistor) line
  over the NMOS ID vs. VDS family of
  characteristic
• with VGS as a parameter.
• Each value of VGS VIN for the inverter gives a
  different drain characteristic curve

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Voltage Transfer Characteristic

• Ordered pairs of points (VGS, VDS) are read from
  the intersection of the output load line with the
  family of curves.
• These are in turn plotted on VDS vs. VGS
• VTC is the resulting curve through these points.
• Gives a value of VDS VOUT for one value of
  input voltage.
• ? can plot VOUT vs. VIN

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Voltage Transfer Characteristic

• Drain Characteristics and Resistor Load Line

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Voltage Transfer Characteristic

• When a logic 1 represented by VOH appears at the
  input of this inverter
• transistor is driven in conduction along upper
  line of drain I-V characteristic
• with proper design logic low level VOL falls
  below transistor threshold voltage
• ? a following inverter stage will be
  non-conducting

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Voltage Transfer Characteristic

• When a logic 0 represented by VOL appears at the
  input of this inverter. ? opposite effect (see
  diagram below)

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Voltage Transfer Characteristic

• This qualitative analysis gives an insight into
  the operation of Q0 for the resistor loaded NMOS
  inverter.
• In the output state, Q0 turns on in the
  saturation region of operation.
• For the output low state Q0 is in the linear
  region
• The state of the Q0 can be determined for the
  other critical points also.

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VOL

• The output high voltage level VOH is already
  known to be VDD.
• The output low voltage level VOL is found by
  equating the currents in the transistor and load
• assuming that input of the transistor is driven
  by the output high level VOH of another identical
  inverter

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VOL

• Transistor assumed to be linear region of I-V
  characteristics
• ?
• i.e. a quadratic and can be solved for .
•        Take only the positive roots (physical
  significance)

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VOL

• If VOL is sufficiently small ( lt 0.4 V)
• ? can neglect the ( )2 term
•  
• ?
•  
• The magnitude of the RL term can be considered.
•  
• Since ? is typically in the range 10 ?A/V2 ? 100
  ?A/V2
• ? to obtain a low value for VOL
• RL must be at least 10k? ?100k?
• Consequently, the primary design flaw for the
  resistor loaded NMOS inverter
• large value for RL required.
• IC resistors of this magnitude require enormous
  silicon areas.

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Calculation of VIL

• Critical points VIL and VIH are defined as the
  points at which
• the negative sign is needed as is an inverter
• VIN increases ? VOUT decreases.
•  

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Voltage Transfer Characteristic
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Calculation of VIL

•  
• At VIN VIL
• ? Output voltage is VOH (near VDD)
• ? Transistor operating in saturation mode

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Calculation of VIL

• Substituting VDS VOUT, the resistor current is
  obtained as
• with and
• ?
• or

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Calculation of VIL

• Solving for

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Calculation of VIL

• rearranging we have
• ?
• NOTE the input low voltage is
• slightly above the threshold voltage
• independent of VDD

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Calculation of VIH

• For MOS logic family, input high voltage VIH is
  defined as
• The point on the VTC before VOL.
• At VIN VIH
• ? transistor operating in linear mode
•  
• Substituting VGS VIH and VDS VOUT into the
  linear drain current expression

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Calculation of VIH

• The resistor current is still given by
• With ID ID(VIN , VOUT)
• IRL IRL (VOUT)
• Equate differentials of the drain and resistor
  current
•  

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Calculation of VIH

• or
•  
• solving for
• ?
•  
• rearranging
•  

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Calculation of VIH

• Substituting the derivatives gives
• The effective load resistance
• Neglect the effect of RL, negligible compared to
  others.
• ?
• Output voltage corresponding to a input high
  voltage

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Calculation of VIH

• The explicit value of VIN VIH and the
  corresponding value of VOUT can be found
• substituting in the linear region drain current
  equation
• re-arranging gives a quadratic in VIH - VT

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Calculation of VIH

• Solve for VIH - VT gives a solution for VIH and
  the corresponding VOUT

Homework !
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Active Load

• The 100k? resistor in the example above is needed
  to limit power consumption.
• It would require a large amount of chip area if
  realised in a standard MOS process
•  
• Sheet resistances available in standard processes
  are in the range 20-100? per square.
• Assuming 100? per square
• A resistor width of 5 ?m
• ? RL would be 5000 ?m long
• ? It would occupy an area 100 times that of the
  transistor

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Active Load

• But the required resistor
• Where often called the aspect
  ratio.
•  
• However if the transistor aspect ratio
  is increased to reduce the size of RL
• proportional increase in transistor size and
  operating current
• One solution is to use small area, high valued
  resistors formed by additional special processes
•   Only used in some LSI systems, never in VLSI

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Active Load

• The alternative way is to use small transistors
  to perform the function of a load resistor.
•  
• Enhancement-mode NMOS transistors can be used as
  load elements operating in either saturation or
  linear regions.
• Were the only forms of transistor load in
  single-polarity MOS circuits before depletion
  mode transistors became feasible with
  ion-implementation in the 1970s.
• Better circuit performance and smaller circuit
  area are obtained using depletion mode NMOS
  transistors as load elements.

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Saturated Enhancement Load

• A single NMOS transistor can be used as a load
  device
• with gate connected to drain
• Note The body is grounded as it is common to
  all transistors in a single chip.

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Saturated Enhancement Load

• Because VGS VDS
• the load transistor can operate only in
  saturation and cut-off. i.e. VDS VGS gt VGS -
  VT

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Saturated Enhancement Load

• QUESTION
• What is the value of ? for an enhancement-mode
  load transistor, with VT 1 so that it will
  provide the same current for VDD 5V, VOL 0.3V
  as the 100k? resistor described in the
  resistor load case above ?.
• where K 20?A/V2 and
• the inverter has an aspect ratio of 2.0.

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Saturated Enhancement Load

• As the load transistor is in saturation
•  
•  
• ?

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Saturated Enhancement Load

• The load line construction and the VTC for the
  inverter with this enhancement load are
• Drain Characteristic and Load Line

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Saturated Enhancement Load

• Voltage Transfer Characteristic

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Saturated Enhancement Load

• ?
• ? This is larger than the inverter device.
•  
• If the minimum allowed dimension is
• The inverting device has aspect ratio of 2 ?
• ? The load device will have and

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Geometry or Beta Ratio

• From equation
• both and scale linearly with the drain
  current ID in the load.
•  
• Because of this fact
• ? the aspect ratio for each transistor
  may be multiplied by the same factor without
  affecting voltage levels.
• Of course the operating current will be
  multiplied by the same factor

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Geometry or Beta Ratio

• The geometry or beta ratio for a MOS device
  inverter is defined as
•  
• If the designer is free to adjust the operating
  current of inverters and gates
• ? a minimum area layout will usually be achieved
  with device size chosen so that the geometric
  mean of the inverter and load aspect ratio
  is unity
• By reducing the value of also reduces the
  circuit area.

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Geometry or Beta Ratio

• One serious deficiency of the enhancement load
  has been overlooked so far.
• The output high level VOH is no longer equal to
  VDD as it was for the resistor load.
• The load transistor ceases to conduct after its
  gate source voltage decreases to the threshold
  voltage
• ? in this case the output mode does not rise
  above
• ? the threshold voltage of the load device is no
  longer as it is for the inverter
• as the full output voltage appears as a body-bias
  between the source and body of the load device

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Geometry or Beta Ratio

• The threshold voltage is now given by
• A recomputation shows that the value of
  needed to achieve is considerably
  increased if is reduced from 5 to 3.5 V.
• These circumstances make it difficult to design
  simple enhancement load static inverters and
  gates which will operate with safe noise margins
  on a 5V supply.

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Linear Enhancement Load

• From the analysis of the saturated load inverter
• Output node can rise to a threshold drop below
  VDD before the load devices ceases to conduct.
• i.e.
•  
• The output voltage of an enhancement-only loaded
  NMOS inverter can be raised to VDD by using a
  load that operates in the linear region.
• Can be accomplished by applying a separate larger
  voltage source to the gate of the load
  transistor.
• This is one reason why early MOS circuits
  required higher voltage supplies.

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Linear Enhancement Load
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Linear Enhancement Load

• To operate in the linear region
• ?
•  
• ? The gate voltage should satisfy
•  
•  
• Thus the circuit is a linear enhancement loaded
  NMOS inverter when the above condition is met.
• ? load device operates in the linear region over
  the entire range of VOUT.
• ? since throughout this range the load device
  is operating with
•  

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Linear Enhancement Load

• The load line construction for this type of
  inverter
• Drain Characteristic and Load Line

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Linear Enhancement Load

• Voltage Transfer Characteristic

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Linear Enhancement Load

• Many different names are applied to this mode of
  operation
• linear load - despite the considerable
  curvature to the load line
• non-saturated load
• triode load
•  
•  
• The linear-enhancement load has several
  disadvantages when used in static inverters and
  gates
• More chip area is required, since extra voltage
  source VGG with associated additional
  interconnections on the chip are needed.
• The required value of is even larger than for a
  saturated enhancement load.

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Depletion load

• Depletion loads overcome the disadvantages
  described above
• At the relatively minor expense of special masked
  ion-implementation step to create the depletion
  device.
• So-called enhancement-depletion (E-D) NMOS
  technology is the basis for the most
  microprocessors and microprocessor peripheral
  devices and static NMOS memories.

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Depletion load

• I-V characteristics of the ideal and a practical
  depletion load device.
• Drain Characteristic and Load Line

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Depletion load

• Voltage Transfer Characteristic

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Summary

• Need to be conscious when designing ICs of area
  and power.
• Resistive loads necessary for baising are very
  wasteful
• Use MOS transistors as load elements.