MAKING A

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MAKING A MODEL

• BOB PEDDENPOHL
• MODELING MANAGER
• CYPRESS MODELING CENTER
• LEXINGTON, KY

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OUTLINE

• WHAT DOES CY KENTUCKY DO?
• WHAT IS A BSIM SPICE MODEL?
• HOW TO MAKE A MOS SPICE MODEL?

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DESIGN KIT MAKES MONEY
DESIGN KIT (CAD, RD) DESIGN KIT (CAD, RD) DESIGN KIT (CAD, RD) PRODUCT ()
PRE-SILICON WORK SILICON QUAL MODELS CIRCUIT DESIGN
SCHEMATICS LAYOUTS DRC LVS E-TEST MODULES TEST CHIP TAPEOUT PRODUCT PLANS MEAS. VTH IDS METAL THICK ILD THICK SPICE RCX MARKET NEEDS PRODUCT SPECS CIRCUIT SCHEMATIC LAYOUT
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DESIGN KIT MAKES MONEY
DESIGN KIT (CAD, RD) DESIGN KIT (CAD, RD) DESIGN KIT (CAD, RD) PRODUCT ()
PRE-SILICON WORK SILICON QUAL MODELS CIRCUIT DESIGN
SCHEMATICS LAYOUTS DRC LVS E-TEST MODULES TEST CHIP TAPEOUT PRODUCT PLANS MEAS. VTH IDS METAL THICK ILD THICK SPICE RCX MARKET NEEDS PRODUCT SPECS CIRCUIT SCHEMATIC LAYOUT
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OUTLINE

• WHAT DOES CY KENTUCKY DO?
• WHAT IS A BSIM SPICE MODEL?
• HOW TO MAKE A MOS SPICE MODEL?

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INTRODUCTION MODELS

• GENERIC DEFINITION
• MAN MADE EXPRESSIONS TO REPRESENT MOTHER NATURE
• VLSI DESIGN DEFINITION
• MODELS DESIGNERS PERCEPTION OF TECHNOLOGY
• ENGINEERING DEFINITION
• MODELS PHYSICAL EQUATIONS PARAMETERS Ids
  BETA (Vgs-VT)2
• where VT 0.6 BETA w/lCOXMOBILITY
  1E-6

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INTRODUCTIONTYPES OF MODELS
SIMULATION MODELS
TABLE LOOKUP
NUMERICAL
SIMULATORS ACCESS MEASURED DC/AC DATA IN A
TABULAR FORM
NUMERICAL SOLUTION OF DEVICE CHARACTERISTIC
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SCHEMATICS USE BSIM COMPACT MODELS
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INTRODUCTION MODELS LIMITATIONS
IDEAL VS REALITY IDEAL DESIGN SIMULATIONS
EXACTLY EQUAL SILICON MEASUREMENTS
REALITY MODEL NOT PERFECT MODEL HAS ACCURACY
LIMITATIONS GOOD DESIGNER UNDERSTANDS MODEL
LIMITATIONS NEED TO MODEL PROCESS VARIATIONS NEED
MODELS QUICKLY TO ENABLE DESIGNERS
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OUTLINE

• WHAT DOES CY KENTUCKY DO?
• WHAT IS A BSIM SPICE MODEL?
• HOW TO MAKE A MOS SPICE MODEL?

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WHAT MODELS USED AT UK?

• WHAT CY TECHNOLOGY DID YOU USE?
• RAM7 Wmin/Lmin 0.42/0.20um, Vcc1.8V, Idrive
  9.99 mA
• WHEN WAS TECHNOLOGY QUALIFIED?
• MODEL FROZEN Q302
• WHAT TYPE OF MOSFETS?
• LV MOS (NSHORT/PSHORT), LVT PMOS (PLOWVT)
• CELL FETS (NPASS, NPD, PPU)
• WHATS NSHORT ELECTRICAL TOX? JUNCTION DEPTH?
• TOX 41 A, XJ 0.1um

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MODEL DEVELOPMENT PROCESS
SELECT GOLDEN WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA RELEASE TO DESIGN
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SELECT GOLDEN WAFER

• IDEAL MODELING SILICON CLOSE TO NOMINAL
• REALITY 400 PARAMETERS, ONLY MOST IMPORTANT
  ON TARGET

NOMINAL
MIN
MAX
WAFER
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MODEL DEVELOPMENT PROCESS
SELECT GOLDEN WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA RELEASE TO DESIGN
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MEASUREMENTS HARDWARE SOFTWARE
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MEASUREMENTS COMPLETE MOS

• FET DC (VTH0, RDSW)
• FET AC (CGDO,DLC)
• DIODE DC (JS,JSW)
• DIODE AC (CJ, CJSW)

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MEASUREMENTS FET DC
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MEASUREMENTS FET DC
MODEL NEEDS SCALE WITHIN ALL GEOMETRY, TEMP
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MEASUREMENTS DC FET QA, VTH VS. L

• MODEL ACCURACY ltgt MEASUREMENT ACCURACY
• CONDENSED DATA TRENDS

Strong Halo , L dependence
Normal SCE
Halo with SCE
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MEASUREMENTS DC FET QA, VTH VS. W

• MODEL ACCURACY ltgt MEASUREMENT ACCURACY
• CONDENSED DATA TRENDS

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MEASUREMENTS FET AC
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MEASUREMENTS DIODE DC/AC
REVERSE BIAS DC CHARACTERISTIC
REVERSE BIAS AC CHAR. f(CJA, CJP, EX,)
I_FORWARD mA
I_Reverse pA
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MEASUREMENTS TRANSIENT

• RING OSCILLATOR VALIDATION OF MODEL

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MODEL DEVELOPMENT PROCESS
SELECT GOLDEN WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA RELEASE TO DESIGN
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WAFER CASE DC MOS EXTRACTION

• MODEL EQUATIONS PARAMETERS
• EQUATIONS (BSIM3V3) MODEL PARAMETERS WAFER
  CASE MODEL

Mobility Model
Threshold Model
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WAFER CASE MOS MODEL BINNING
Long/Wide Constant Vt
Short Channel Effects (HALO/DIBL)
Narrow Width Effects (STI/LOCOS)
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WAFER CASE AC FET DIODE

• MODEL EXTRACTION
• MODEL EQUATIONS PARAMETERS
• EQUATIONS (BSIM3V3) PARAMETERS (EXTRACTED FROM
  MEASUREMENTS) MODEL (WAFER CASE)

MOSFET CV MODEL
Accumulation
MOS DIODE IV MODEL
Inversion
BSIM3 Limitation
Intrinsic Cap for Analog Design
MOS DIODE CV MODEL
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MODEL DEVELOPMENT PROCESS
SELECT GOLDEN WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA RELEASE TO DESIGN
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RO CAL LAYOUT EXTRACTED SIMULATION

• VALIDATE CAD EXTRACTION RULES MOS BSIM MODELS

R10
C9
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MODEL DEVELOPMENT PROCESS
SELECT GOLDEN WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA RELEASE TO DESIGN
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CORNER MODELS

• WAFER CASE SIMULATIONS WAFER MEASUREMENTS
• WHAT ABOUT PROCESS VARIATIONS?
• WILL MY DESIGN YIELD?

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CORNER MODELS
REALITY EVERY SITE/WAFER/LOT/SPLIT IS DIFFERENT
( PROCESS VARIATIONS)
WORKING WITH REALITY CORNERS MODELING SPACE TO
COVER ALL POSSIBILITIES (STATISTICALLY) IN
PROCESS
TEAM EFFORT TO GET GOOD YIELD FAB /-4 SIGMA
E-TEST ? 99.99 WAFERS INSIDE MIN/MAX MODELING
MIN/MAX MODELS MATCH FAB LIMITS DESIGN SIMULATE
DESIGN WORKING AT MIN/MAX LIMITS ALL 3 GROUPS
WORKING GOOD PRODUCT YIELD
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WHY 5 MOS CORNERS?
fs
ss
sf
ff
tt
tt
ff
sf
ss
fs
VTXNS15 vs. VTXPS15 (V) (Vth _at_ W/L25/0.15um)
IDSNS15 vs. IDSPS15 (mA) Idrive
(VgsVdsVcc) W/L25/0.15um

• VTs AT SS FF 70 SPEC RANGE
• VTs AT FS/SF 100 SPEC RANGE

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WHY CORNER METHODOLOGY IMPORTANT

• MODEL MUST MATCH DESIGN/FAB AGREED LIMITS
• FAB WANTS WIDE MIN/MAX LIMITS
• STATISTICAL PROCESS CONTROL (SPC)
• HOW GOOD DOES A PROCESS RUN WITHIN ITS
  NOM/MIN/MAX
• DESIGN WANTS NARROW MIN/MAX LIMITS
• EASIER TO DESIGN
• SMALL PROCESS VARIATION ? SMALLER SI AREA

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MODEL DEVELOPMENT PROCESS
SELECT GOLDEN WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA RELEASE TO DESIGN
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QA MODEL DOCUMENTATION

• MODEL SUMMARY TABLE
• MODEL ACCURACY IN SUB-THRESHOLD, GM ACCURACY

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APPENDIX

• BOB PEDDENPOHL (PED)
• CYPRESS MODELING CENTER

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Applying the Corner Models
Design
Interconnects/Passives trtc, hrlc, lrhc
FET Corners tt, ff, ss, sf, fs
CellFET Corners ttcell, ffcell, sscell
Npass Nlatch Platch
Nmos/Pmos Nthick/Pthick (HV) Diode PNP
Interconnect R tres, fres, sres
Interconnect C tpar, fpar, spar
rc.mod
Temp coef of R
metal/contact/poly/diff Sheet resistances
C for various line/space