DESIGN IMPLEMENTATION

1
DESIGN IMPLEMENTATION

• Design Flow
• Prototyping Tips
• Basic Built-In Self-Test
• Debouncing External Switches
• Filtering an Input to Produce a Single Pulse
• Hierarchy with Submodule Components
• Synchronizing External Inputs

2
DESIGN FLOW
3
DETERMINE SYSTEM I/O REQUIREMENTS
4
DECOMPOSE EACH LEVEL INTO 7/-2 SUBMODULES
5
SYNTHESIZE AND SIMULATE EACH SUBMODULE AND THEN
INTEGRATE THEM
6
GENERATE THE PHYSICAL LAYOUT
7
DESIGN STEPS (part 1)

• 1. Analyze the requirements of the application.
• 2. Develop the initial architectural
  specifications.
• 3. Decompose the design into 7/-2 manageable
  blocks at each level of the hierarchy from top to
  bottom.
• 4. Develop structural VHDL for each level to
  show the interconnections of submodules.
• 5. Develop the VHDL code for each submodule.

8
DESIGN STEPS (part 2)

• Compile and test each VHDL submodule individually
  (You may find it easier to enter the design
  bottom-up).
• Integrate previously tested submodules and test
  all of them together at each level.
• Generate the physical layout of the entire
  design.
• Perform a post-layout simulation of the entire
  design.
• Download the configuration file to the prototype
  board to demonstrate the working design.

9
DESIGN FLOW
10
ALTERA PROTOTYPING BOARD
11
BASIC BUILT-IN SELF-TEST

• Downloading bist_alt ensures the integrity of the
  connection between the CPU and the Altera
  prototyping board AND then checks one input
  switch and both 7-segment displays.
• More thorough checks could be added to ensure the
  integrity of the board I/O for a specific
  project.

12
INTERNAL FREQUENCIES CAN BE DERIVED FROM THE
EXTERNAL CLOCK

• A crystal oscillator on the Altera prototyping
  board produces a 25.175 Mhz clock that
  synchronizes all flip-flops internal to the
  Altera part.
• Counters can be used to divide down one frequency
  into a slower synchronized one

Divide By Frequency Duration 25 clock_1MHz 1
ns 10 clock_100KHz 10 ns 10 clock_10KHz 100
ns 10 clock_1KHz 1 ms 10 clock_100Hz 10
ms 10 clock_10Hz 100 ms 10 clock_1Hz 1 s
13
clk_div.vhd (part 1)

• LIBRARY IEEE
• USE IEEE.STD_LOGIC_1164.all
• USE IEEE.STD_LOGIC_ARITH.all
• USE IEEE.STD_LOGIC_UNSIGNED.all
• ENTITY clk_div IS
• PORT
• (
• clock_25Mhz IN STD_LOGIC
• clock_1MHz OUT STD_LOGIC
• clock_100KHz OUT STD_LOGIC
• clock_10KHz OUT STD_LOGIC
• clock_1KHz OUT STD_LOGIC
• clock_100Hz OUT STD_LOGIC
• clock_10Hz OUT STD_LOGIC
• clock_1Hz OUT STD_LOGIC)
• END clk_div

14
clk_div.vhd (part 2)

• ARCHITECTURE a OF clk_div IS
• SIGNAL count_1Mhz STD_LOGIC_VECTOR(4 DOWNTO 0)
  
• SIGNAL count_100Khz, count_10Khz, count_1Khz
  STD_LOGIC_VECTOR(2 DOWNTO 0)
• SIGNAL count_100hz, count_10hz, count_1hz
  STD_LOGIC_VECTOR(2 DOWNTO 0)
• SIGNAL clock_1Mhz_int, clock_100Khz_int,
  clock_10Khz_int, clock_1Khz_intSTD_LOGIC
• SIGNAL clock_100hz_int, clock_10Hz_int,
  clock_1Hz_int STD_LOGIC
• BEGIN
• PROCESS
• BEGIN
• -- Divide by 25
• WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz
  '1'
• IF count_1Mhz lt 24 THEN
• count_1Mhz lt count_1Mhz 1
• ELSE
• count_1Mhz lt "00000"
• END IF
• IF count_1Mhz lt 12 THEN
• clock_1Mhz_int lt '0'

15
clk_div.vhd (part 3)

• -- Divide by 10
• PROCESS
• BEGIN
• WAIT UNTIL clock_1Mhz_int'EVENT and
  clock_1Mhz_int '1'
• IF count_100Khz / 4 THEN
• count_100Khz lt count_100Khz 1
• ELSE
• count_100khz lt "000"
• clock_100Khz_int lt NOT clock_100Khz_int
• END IF
• END PROCESS
• -- Divide by 10
• PROCESS
• BEGIN
• WAIT UNTIL clock_100Khz_int'EVENT and
  clock_100Khz_int '1'
• IF count_10Khz / 4 THEN
• count_10Khz lt count_10Khz 1
• ELSE
• count_10khz lt "000"

16
clk_div.vhd (part 4)

• etc
• -- Divide by 10
• PROCESS
• BEGIN
• WAIT UNTIL clock_10hz_int'EVENT and
  clock_10hz_int '1'
• IF count_1hz / 4 THEN
• count_1hz lt count_1hz 1
• ELSE
• count_1hz lt "000"
• clock_1hz_int lt NOT clock_1hz_int
• END IF
• END PROCESS
• END a

17
AN INPUT SWITCH MAY BOUNCE
18
debounce.vhd (part 1)

• LIBRARY IEEE
• USE IEEE.STD_LOGIC_1164.all
• USE IEEE.STD_LOGIC_ARITH.all
• USE IEEE.STD_LOGIC_UNSIGNED.all
• -- Debounce Pushbutton Filters out mechanical
  switch bounce for around 40Ms.
• ENTITY debounce IS
• PORT(pb, clock_100Hz IN STD_LOGIC
• pb_debounced OUT STD_LOGIC)
• END debounce

19
debounce.vhd (part 2)

• ARCHITECTURE a OF debounce IS
• SIGNAL SHIFT_PB STD_LOGIC_VECTOR(3 DOWNTO
  0)
• BEGIN
• -- Debounce clock should be approximately 10ms
  or 100Hz
• PROCESS
• BEGIN
• WAIT UNTIL (clock_100Hz'EVENT) AND
  (clock_100Hz '1')
• -- Use a shift register to filter switch
  contact bounce
• SHIFT_PB(2 DOWNTO 0) lt SHIFT_PB(3 DOWNTO 1)
• SHIFT_PB(3) lt NOT PB
• IF SHIFT_PB(3 DOWNTO 0)"0000" THEN
• PB_DEBOUNCED lt '0'
• ELSE
• PB_DEBOUNCED lt '1'
• END IF
• END PROCESS
• END a

20
BEHAVIOR OF debounce.vhd

• CLOCK PB SHIFT_PB PB_DEBOUNCED
• 1 0000 0
• 0 0000 0
• 1 1000 1
• 0 0100 1
• 0 1010 1
• 0 1001 1
• 1 1000 1
• 1 0000 0

21
FILTERING AN INPUT TO PRODUCE A SINGLE PULSE
22
onepulse.vhd (part 1)

• LIBRARY IEEE
• USE IEEE.STD_LOGIC_1164.all
• USE IEEE.STD_LOGIC_ARITH.all
• USE IEEE.STD_LOGIC_UNSIGNED.all
• -- Single Pulse circuit
• -- the output will go high for only one clock
  cycle
• ENTITY onepulse IS
• PORT(PB_debounced, clock IN STD_LOGIC
• PB_single_pulse OUT STD_LOGIC)
• END onepulse

23
onepulse.vhd (part 2)

• ARCHITECTURE a OF onepulse IS
• SIGNAL PB_debounced_delay, Power_on STD_LOGIC
• BEGIN
• PROCESS (Clock)
• BEGIN
• WAIT UNTIL (CLOCK'event) AND (CLOCK'1')
• -- Power_on will be initialized to '0' at
  power up
• IF Power_on'0' THEN
• -- This code resets the critical signals once
  at power up
• PB_single_pulse lt '0'
• PB_debounced_delay lt '1'
• Power_on lt '1'
• ELSE

24
onepulse.vhd (part 3)

• -- A single clock cycle pulse is produced when
  the switch is hit
• -- No matter how long the switch is held down
• -- The switch input must already be debounced
• IF PB_debounced '1' AND PB_debounced_delay
  '0' THEN
• PB_single_pulse lt '1'
• ELSE
• PB_single_pulse lt '0'
• END IF
• PB_debounced_delay lt PB_debounced
• END IF
• END PROCESS
• END a

25
HIERARCHY WITH SUBMODULE COMPONENTS
clock_25Mhz
26
hierarch.vhd (part 1)

• LIBRARY IEEE
• USE IEEE.STD_LOGIC_1164.all
• USE IEEE.STD_LOGIC_ARITH.all
• USE IEEE.STD_LOGIC_UNSIGNED.all
• ENTITY hierarch IS
• PORT (clock_25Mhz, pb1 IN STD_LOGIC
• pb1_single_pulse OUT STD_LOGIC)
• END hierarch
• ARCHITECTURE a OF hierarch IS
• -- Declare internal signals needed to connect
  submodules
• SIGNAL clock_1MHz, clock_100Hz, pb1_debounced
  STD_LOGIC
• -- Use Components to Define Submodules and
  Parameters
• COMPONENT debounce
• PORT(pb, clock_100Hz IN STD_LOGIC
• pb_debounced OUT STD_LOGIC)
• END COMPONENT

27
hierarch.vhd (part 2)

• COMPONENT onepulse
• PORT(pb_debounced, clock IN STD_LOGIC
• pb_single_pulse OUT STD_LOGIC)
• END COMPONENT
• COMPONENT clk_div
• PORT(clock_25Mhz IN STD_LOGIC
• clock_1MHz OUT STD_LOGIC
• clock_100KHz OUT STD_LOGIC
• clock_10KHz OUT STD_LOGIC
• clock_1KHz OUT STD_LOGIC
• clock_100Hz OUT STD_LOGIC
• clock_10Hz OUT STD_LOGIC
• clock_1Hz OUT STD_LOGIC)
• END COMPONENT

28
hierarch.vhd (part 3)

• BEGIN
• -- Use Port Map to connect signals between
  components in the hierarchy
• debounce1 debounce PORT MAP (pb gt pb1,
  clock_100Hz gt clock_100Hz, pb_debounced gt
  pb1_debounced)
• prescalar clk_div PORT MAP (clock_25Mhz gt
  clock_25Mhz, clock_1MHz gt clock_1Mhz,
  clock_100hz gt clock_100hz)
• single_pulse onepulse PORT MAP (pb_debounced gt
  pb1_debounced, clock gt clock_1MHz,
• pb_single_pulse gt pb1_single_pulse)
• END a

29
HIERARCHY WITH SUBMODULE COMPONENTS
clock_25Mhz
30
SYNCHRONIZERS REDUCES RISK OF METASTABILITY
PROBLEMS

• Signals from external sources such as switches or
  another circuit whose clock is independent must
  be synchronized with our internal clock.
• If not, the external input may occur during the
  decision window of our flip-flop and cause it to
  go into a metastable state.
• To reduce the likelihood of this occurring, the
  input can be double-buffered.