Offchip Decoupling Capacitor Allocation for Chip Package CoDesign

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Off-chip Decoupling Capacitor Allocation for Chip
Package Co-Design

• Hao Yu
• Berkeley Design Automation
• hao.yu_at_berkeley-da.com

• Chunta Chu and Lei He
• EE Department
• UCLA

The work was performed at UCLA and was partially
supported by NSF and UC-MICRO
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Decap Allocation for Clean Power Delivery

• Chip-package co-design requires a noise-free
  off-chip power delivery system (PDS)
• Modeling inductance is a must
• Decoupling capacitors (decaps) are allocated on
  chip-package interface to satisfy power
  integrity
• It is a challenging task tofind a fast yet
  accuratedecap allocation for a large-scale design

How to consider the large and complex
physical-level layout during the system-level
design?
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Physical Level Challenge

• Finite parastic impedance affects the circuit
  functionality at chip-package interface
• Supply volatage drop and electromagnetic (EM)
  coupling
• Distributed post-layout model burdens the
  system-level power integrity analysis and design
• Millions of nodes and terminals with dense
  inductances

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System Level Challenge
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The Need of Macromodeling

• Representing a large and complex power delivery
  system blindly leads to expensive design cycles
• A compact representation by macromodeling is
  needed

• Existing decap allocation methods with
  macromodeling ZhengCICC04, ChenISPD06
• Generate PDS macromodel
• Apply simulated annealing to add/remove one decap
  to alegal position
• Can not efficiently handle alarge-scale design

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Limitations of Existing Macromodeling
How to use it ?
project

• Macromodeling algorithms PVL, PACT, PRIMA are
  limited to handle a large-scale PDS
• Become ineffective when terminal number is large
• Do not provide the sensitivity information
• Destroy the structure of state matrix

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Our Decap Problem Formulation

• A multiple-ring-based problem formulation
• Represent decap solutionby combination of
  multi-level templates
• Constrain by noise integral at I/O instead of
  noise amplitude in ChenISPD06
• Optimization Method
• Each step inserts a template with a given decap
  type based on sensitivity instead of
  simulated-annealing

The key is to efficiently calculate sensitivity
from macromodel
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TBS2 Macromodeling for PDS

• Principle Terminal Selection
• Capture the essential input/output behavior
• Parameterization
• Compute performance sensitivities from the layout
  modifications
• Structured Simulation
• Sparsely arrange couplings (sparsity), leverage
  diverse physical domains (latency) and analyze at
  block-levels (hierarchy)

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TBS2 (1) Principle Terminal Selection

• The input signals (J B x I) are temporally
  correlated
• Described by a correlation matrix C (N x N)

• Correlated terminals b0 b1 b2 can be
  simplified with use of a principal component
  analysis (PCA)

• Select K principle terminals by K-means method

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TBS2 (2) Parameterization

• Decaps can be parametrically described by
• The sizing vector (D) for M2 types of decaps and
  the topological matrix (X) for M1 levels of rings

X(2,6)
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TBS2 (2) Structured Stamping

• Partition the nominal state matrices according to
  clustered terminals
• Triangularize the partitioned state matrices
• Triangularize the nominal and sensitivity states
  in each local block
• Details can be found TBS1YuDAC06 and
  YuISLPED06

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TBS2 (3) Structured Macromodeling
Block-wise nominal and sensitivity
Details can be found in TBS1 YuDAC06 and
YuISLPED06
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Improved Accuracy By TBS2 Reduction
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Our Decap Algorithm Overview

• Apply TBS2 just one-time to generate a structured
  and parameterized macromodel
• Calculate block-level nominal noise at each
  terminal and its sensitivity w.r.t the
  partitioned template
• Check if noise integral satisfies constraints
• Allocate decaps for each block according to the
  sensitivity in a greedy fashion

Calculate nominal sensitivity
update Template
Check Constraints
TBS2
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Reduced Runtime and Cost of Decap Allocation
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Conclusions