MsCAD UW MixedSignal CAD Research and Education

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MsCAD UW Mixed-Signal CAD Research and Education

• Professor Richard Shi
• Department of Electrical Engineering
• University of Washington, Seattle WA
• shi_at_ee.washington.edu

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Mixed-Signal CAD Research Faculty
Prof. Richard Shi Modeling/Simulation,
VHDL-AMS, Layout, Extraction Prof. David
Allstot Parasitic-aware optimization,
substrate modeling Prof. Carl Sechen
High-performance layout, symbolic analysis,
CAD for high-performance digital
circuits Prof. Mani Soma Fault
simulation and test generation Prof. Vikram
Jandhyala Full-wave simulation,
parasitics extraction Prof. Sumit Roy
Modeling and optimization of communication
circuits Prof. Scott Dunhum
Technology/process CAD
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Mixed-Signal CAD Graduate Students
Ph.D. Candidates Alicia Manthe (SRC/Intel
Fellow) Symbolic circuit analysis
Distortion/nonlinearity analysis Zhao Li
(SRC) Substrate modeling of RF transistors,
distortion Yong Wang (DARPA) Coupled
EM/Circuit simulation, parasitic
extraction and reduction, VHDL-AMS
behavioral modeling Sambuddha Bhattacharya
(NSF-ITR) Parasitic-aware layout synthesis
and reuse, block delay calculation,
switching noise analysis Wan Bo (DARPA) Fast
mixed analog and digital simulator, parallel
and distributed simulation Bo Hu
(DARPA) Behavioral model generation
nonlinear model reduction Nuttorn
Jadgkrajarng (DARPA, Internship with Intel)
Decoupling Lei Yang (DARPA) Behavioral
modeling
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Mixed-Signal CAD Research Students
Master Candidate Michael Greaves
(Co-supervised with David Allstot) Impact of
Substrate Coupling Under Process Variations
for High-Frequency CMOS Circuits Roy
Harmoto Layout Analysis and Visualization of EM
Effects Undergraduate Research Assistants
Brigette Huang Model generation from
simulation/measurement data Amedee Beaudoin
Visualization of layouts and EM Simulation
Samuel Ting EM simulation and extraction
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Mixed-Signal CAD Research Projects
CoSMoS Coupled Modeling and Simulation of
Systems-on-Chips Sponsor
DARPA PIs Richard Shi, Vikram Jandhyala,
David Allstot Subcontractors Lawrence
Livermore National Lab., Boeing Period July
1, 2001 to June 30, 2004 Industry
Collaborators Motorola, Intel Objectives
a coupled hierarchical modeling and fast
simulation capacities for
systems-on-chip signoff simulation
with the emphasis on predicting substrate
coupling and full-wave
power-ground noises Target Applications
multiple transceivers on chips
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Mixed-Signal CAD Research Projects
NSF CAREER Behavioral Modeling and
Simulation Sponsor NSF
PIs Richard Shi Period July 1, 2001 to June
30, 2004 Objectives Methods and
algorithms for automatic behavioral
modeling and simulation
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Mixed-Signal CAD Research Projects
Symbolic Circuit Analysis and Modeling of
Analog/RF Circuits Sponsor
DARPA PIs Richard Shi Period July 1,
2001 to June 30, 2004 Industry
Collaborators Motorola, Intel Objectives
Symbolic analysis of analog/RF circuits
Target Applications analog/RF circuit block
modeling
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Mixed-Signal CAD Research Projects
Substrate Modeling of CMOS RF Transistors
Sponsor SRC PIs Richard Shi, Karti Mayaram
(OSU) Period July 1, 2001 to June 30, 2004
Industry Collaborators Conexant
Objectives To create layout-dependent models
for RF transistors
including substrate coupling Target
Applications transistor models for Gigahertz RF
applications
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Mixed-Signal CAD Research Projects
Fast Methods for Coupled Circuit/EM/Digital
Simulation Sponsor NSF/SRC PIs
Richard Shi and Vikram Jandhyala Period July
1, 2001 to June 30, 2004 Objectives
Methods and algorithms for fast simulation of
coupled EM,
circuit-level and logic-level models
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Mixed-Signal CAD Research Projects
Application of Communication Theory to Nano
Interconnect Modeling Sponsor NSF/SRC
PIs Richard Shi, Sumit Roy and David Allstot
Period July 1, 2001 to June 30, 2004
Objectives To develop models, based on
communication principles for
interconnects on a noise environment, and to
apply developed models to on-chip
signaling.
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Mixed-Signal CAD Research Projects
Modeling for SoC Integration Sponsor NSF
PIs Richard Shi (PI, David Allstot)
Period July 1, 2001 to June 30, 2004
Objectives Create behavioral models for
analog/RF blocks
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Mixed-Signal CAD Research Projects
Fast Methods for Coupled Circuit/EM/Digital
Simulation Sponsor NSF/SRC PIs
Richard Shi and Vikram Jandhyala Period July
1, 2001 to June 30, 2004 Objectives
Methods and algorithms for fast simulation of
coupled EM,
circuit-level and logic-level models
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Mixed-Signal CAD Education

• EE415 Computer-Aided Circuit Analysis
• EE527 Advanced Circuit Simulation
• EE538C Behavioral Modeling and Simulation
  (Cadence, Mentor, Intel)
• E541 Logic Synthesis
• EE Physical Design Automation

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SoC Modeling and Simulation Challenges

• Multiple functionalities co-exist
• Multiple abstraction levels needed for each block
• Intellectual-Property (IP)-based design layout,
  netlist and behavior spec co-exit
• Multiple tech MEMS, optical
• Too complex to simulate

• Massively coupled
• Interconnect
• Power/ground network
• Substrate coupling

Lumped models too large for Spice simulation and
reduced-order models may not be adequate
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Need for Distributed Effect Modeling
Modeling with Partial differential equations or
Integral equations Model power/ground nets
as PDEs (IBM)

• Full-wave EM needed
• RF components
• Packaging
• GHz on-chip coupling

Problem No Adequate Simulator Leads to Long
Design Cycle Time Over-Conservative Design
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Project Goal and Our Approach
Project Goal Develop system-on-chip
modeling and simulation capacities to
facilitate the design process, assist with noise
identification, and validate design prior to
fabrication.
Our approach Develop a unified language
and solver for directly Coupled Simulation and
Modeling of Systems-on-chips analog
digital EM
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Major Advantages

• Provide a hierarchical, coupled simulation
  methodology
• and implementation based on a language-centric
  description
• Utilize the abstraction and hierarchy for
  efficiency
• Enable Intellectual-Property (IP)-based design
• Facilitate modeling no need to convert PDEs
  to ODEs
• to circuits

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Key Challenges

• A unified language for SoC including distributed
  modeling
• Coupled EM and circuit simulation
• EM modeling and solver capacities for full-chip
  simulation

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Prior Work Leveraged in CoSMoS
behavior
Matlab
architecture
VHDL
blocks
SPICE
SPICE
transistor
Eiger BEM-based EM Modeling cce.llnl.gov/eiger EM
Solve FEM-based 3-D EM www.llnl.gov/casc/projects
/emsolve
device
MHDL
Full-wave Electromagnetics
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CoSMoS Research Tasks Objectives

• To develop a unified language for exact,
  hierarchical, behavioral modeling and simulation
  of giga-scale mixed-signal systems-on-chip
• To develop compilation and simulation
  technologies for coupled modeling of
  discrete-event, continuous-time lumped (ODEs) and
  distributed (PDEs) systems
• To develop advanced EM (PDEs/IEs) solving
  capabilities with 100x speed improvement for
  performance-critical SoC analysis
• To demonstrate and validate proposed
  modeling/simulation technologies in DoD
  electronic system designs

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Minimal VHDL-AMS Extension for Distributed
Effect Modeling
Goal Extend VHDL-AMS to model SoC distributed
effects at the
Maxwell-equation level with the targeted
applications in RF components,
conducting/radiation coupling.
Objectives 1. Support built-in or atomic
approach to EM object modeling
2. Support structural composition to help
description and solving EM coupling ports
Material properties (e µ)
Basic operators (? ?, )
Geometry specification
3. Support EM/circuit interfaces
EM-circuit coupling ports field/(I,V)
interaction equations
Boundary conditions
4. Support frequency-domain modeling s
parameters
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Compilation-Driven Object-OrientedCoSMoS
Simulator Architecture
Intermediate Format
Code Generator
time-domain synchronization
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VEGAS Potential Test Case 58.6GHz 0.6mm CMOS
Distributed Amplifier
Inter/Intra-Chip EM Interaction using Eiger and
Behavioral Modeling

• Research
• Compact passive

CoSMoSparser
behavioral model generator

• Eiger leverages
• object-oriented
• framework
• Greens functions
• boundary conditions

Eiger SoC solver
entity TwoPortEMObject is port (terminal NODE1,
NODE2 ELECTICAL quantity F FORCE)
.. E_STRAIN STRESS/YOUNG_MOD
GAUGE_FACTOR 1 2POISSON_RATIO
RESISTIVITYDOT/E_STRAIN STRESS
F/APPLIED_AREA end architecture BEHAVIORAL

• Specific developments for SoC modeling
• Low frequency solution
• Fast solver for multi-layered media
• Hierarchical geometry meshing

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Substrate Coupling via EMSolve

• EMSolve is a LLNL FEM code framework for solving
  PDEs on unstructured 3D grids
• EMSolve is ideally suited for modeling of
  inhomogeneous substrate effects
• EMSolve can be used for virtually any PDE that
  involves divergence, gradient, and curl operators
• Static, frequency-domain, or time-domain
  simulation modes
• NeoCAD specific research
• O(n) multigrid solvers
• Hierarchical geometry/mesh
• Integration with circuit simulator

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Coupled Circuit and EM Simulation By
Partial-Element Behavioral Modeling (PEBM)
PEEC of Ruehli
Linear ODEs EM/circuit interfacing equations ODEs
for circuits
Research ? language-driven compact modeling
? frequency-domain models for
full-wave time-domain simulation


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Fast Direct Linear/Nonlinear Solver for coupled
circuit and EM simulation
Objectives ? Greens function independent fast
solver ? massive number of
RHS (direct solver)
Equations
low-rank
Automatic Differentiation

• Research
• Structure (Greens function)
• Regularity
• Hierarchical modeling
• Sparsity (spatial temporal)

Sponsored in part by NSF/SRC


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CoSMoS Application Drivers

• Boeing Design Cases
• Optical Data Bus Transceiver (0.25CMOS, 2.5Gbps)
  substrate coupling induced phase noise is the
  limiting factor
• Processor Phase Lock Loops need to predict the
  dominant noise contributors both conducted --
  through supplies, and radiated -- coupling to
  substrate
• 10-Bit 1Gsps A/D Converter linearity, heat,
  jitter, noise
• Phase Array Full-wave EM simulation capacity is
  a must
• MEMS based Wireless Micro Sensor Modules (mixed
  tech)
• UW (Allstot NSF/Information Technology Research
  Initiative)
• Distributed amplifier on-chip inductors
  coupling parasitic-aware optimization is
  essential, 4 days of CPU time for 4 FETs