Bridging Theory in Practice

1
Bridging Theory in Practice

• Transferring Technical Knowledge
• to Practical Applications

2
The ABCs of ESD, EOS, and SOA
3
The ABCs of ESD, EOS, and SOA
4
The ABCs of ESD, EOS, and SOA

• Intended Audience
• Electrical engineers with a knowledge of simple
  electrical circuits
• An understanding of MOSFET devices
• Topics Covered
• What is Electrostatic Discharge (ESD)
• What is Electrical Over Stress (EOS)
• What is Safe Operating Area (SOA)
• Expected Time
• Approximately 90 minutes

5
The ABCs of ESD, EOS, and SOA

• What is ESD
• Where does ESD come from
• MOSFET Gate susceptibility
• Test Standards
• Component level vs. module level tests
• What is EOS
• What is SOA

6
Electrostatic Discharge (ESD)

• We are all familiar with a common form of
  electrostatic discharge (ESD)
• ESD is the sudden transfer of electrostatic
  charge between objects at different electrostatic
  potentials

7
Where Does ESD Come From

• Triboelectric Charging
• Mechanical Contact and Separation
• Walking on carpet

• Direct Charging
• Mobile Charge Transfer Plugging in a cable
  (e.g. USB to PC)

• Ionic Charging
• Not properly balanced Air Ionizer can charge an
  object (instead of intended operation to
  neutralize/balance charge)
• Charged object comes into contact with a grounded
  object (such as machine pick-up probe or grounded
  human operator)
• This is example of charged device model (CDM)
  eventmore to come!!!

8
Where Does ESD Come From?

• Which levels can occur?
• Below 3-4kV you see, hear or feel nothing!
• Just above 4kV, air-gap-sparks can occur
• 1mm 1kV (5mm spark 5kV)

• Why does a 2kV protected device survive the real
  world?
• You are charged relatively to earth, not to
  pin7
• You do not have 4kV between your thumb and your
  index finger

9
Where Does ESD Come From?

• Influence of Air Humidity
• Higher relative air humidity does cause a
  moisture film on surfaces
• Charge is more distributed, lower voltages thus
  occur
• But dry air does not have a higher inherent
  resistance

16
15
ESD Voltage (kV)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
100
5
10
20
30
40
50
60
70
80
90
Relative Air Humidity
10
MOSFET Gate Susceptibility
Source
Drain
Gate
SiO2
n
n
p-type
11
Charge Is Applied to the MOSFET Gate
But, the charge is stuck on gate due to
insulating SiO2
Source
Drain
Gate
SiO2
Cgs
n
n
p-type
12
A Quick Review ofVoltage and Capacitance

• Voltage
• Think of voltage as an amount of possible
  electrical work
• A high voltage means additional electrical work
  is possible
• If the voltage is improperly directed or used,
  unintended (and potentially harmful) work
  will be performed
• Capacitance
• Capacitors are one way of storing electrical
  work/energy
• If a capacitor can store a large amount of
  electrical work, it has a large
  capacitance
• If a capacitor can store only a small amount of
  electrical work, it has a small capacitance

12V
Ground
Battery
13
A Quick Review ofVoltage and Capacitance

• Variables and Constants
• C ? Capacitance ? Permittivity of Silicon
  Dioxide
• Q ? Charge A ? Area of Capacitor Plates
• V ? Voltage d ? Distance Between Conductors
• Two Basic Equations
• Rearranging yields

14
Quick Review Summary

• is a constant for a given material
  (SiO2)
• As the charge (Q) on the capacitor increases -
• the voltage across the capacitor increases.

15
Gate Charge Induces a Gate Voltage
Source
Drain
Gate
Source
Drain
Gate
SiO2
SiO2
n
n
n
n
p-type
p-type
16
Induced Gate Voltage Creates a Hole in the SiO2
Source
Drain
Gate
Source
Drain
Gate
SiO2
SiO2
n
n
n
n
Allowable E-field within SiO2 exceeded
p-type
p-type
17
Induced Gate Voltage Creates a Hole in the SiO2
MOSFET cannot turn on
Source
Drain
Gate
Source
Drain
Gate
Gate-Source Short
SiO2
SiO2
n
n
n
n
p-type
p-type
18
Gate susceptibility summary

• As the charge (Q) on the capacitor increases -
• the voltage across the capacitor increases.
• If the transistor decreases in size -
• the thickness of the SiO2 gate (d) decreases -
• but, the area (A) of the gate decreases faster
  -
• For the same amount of charge, the voltage across
  the capacitor is higher for a smaller transistor
• More advanced technologies may require additional
  ESD precautions

19
Induced Voltage for 3?m and 1.2?m CMOS Processes

• 3?m Process (Minimum Size Transistor)
• tox 400 Å 4x10-8 m
• L 3?m
• W 3?m
• Q 1.16x10-11 C
• 1.2?m Process (Minimum Size Transistor)
• tox 200 Å 2x10-8 m
• L 1.2?m
• W 1.2?m
• Q 1.16x10-11 C

20
ESD Standards Test Overview

• ESD Standards Tests should simulate real
  world events as realistic as possible
• There is no single/one size fits all ESD Test
  available ?Different handling/mounting
  conditions have resulted in different ESD tests
• e.g. car-manufacturers follow different ESD
  standards than component-suppliers both are
  talking about ESD but not about the same applied
  ESD-standards

• Be careful to know complete standard definition
• ESD 2kV, 2kV HBM, does not mean much The
  Standard is missing
• e.g JEDEC22-A114 MIL-STD-883, Method 3015.7,
  (more complete)

21
ESD Standards Tests Overview

• A Standard consists of
• a used MODEL (HBM, MM, )

• VALUES for the elements used in the model
  (R1500 Ohm, C100pF)

• plus TEST PROCEDURE how to apply the standard
  (e.g. 3 pulses)

Standard


Model
Values
Procedure

• Therefore Standards can differ in each subset, in
  the
• MODEL
• VALUES
• TEST PROCEDURE
• HBM 2kV is not specific 2kV JEDEC22-A114
  is better defined

22
ESD Models Human Body Model

• Human Body Model (HBM) consists of a Capacitor
  and a series Resistor
• Values are defined in the specific standard
• Commonly used C 100pf, R1500 Ohm (JEDEC, Mil,
  etc.)
• Test Procedure is defined in the specific
  standard
• Commonly used 1 to 3 pulses, both polarities, 3
  devices/voltage level

• HBM Standards(R1500 Ohm, C100 pF)
• JEDEC JESD 22-A114 2
• Military Standard Mil.883 3015.7 3
• ANSI/ESD STM5.1 4
• IEC 61340-3-1
• Human ESD Model(R2000 Ohm, C150 pF 330 pF)
• ISO/TR 10605 5
• Human Body Representative
• (R330 Ohm, C150 pF)
• IEC 61000-4-2 6

Commonly used for component tests
23
ESD Models Human Body Model ? Waveform

• HBM Jedec22-A1114 Waveform
• 10ns rise time typically (short)
• 2-10ns are allowed
• Peak current
• Rule of Thumb
• 1kV 2/3 Ampere

1kV
24
ESD Models Machine Model

• Machine Model (MM) consists of a Capacitor and no
  series Resistor
• Values are defined in the specific standard
• Commonly used C 200pF,
• Test Procedure is defined in the specific
  standard
• Commonly used 1 to 3 pulses, both polarities, 3
  devices/level

• MM Standards(C200 pf)
• JEDEC JESD 22-A115 11
• ANSI/ESD STM5.2
• Philips Standard(C200 pF, R10-25 Ohm,
  L0.75-2.5µH)
• Standard??

Some definitions use MM standard with a 25 Ohm
series resistor, which at least doubles the
achievable ESD Level!
25
ESD Models Machine Model

• MM stress is similar to HBM
• Oscillations due to setup parasitics
• MM and HBM failure modes are similar
• Less reproducible than HBM

Source T. Brodbeck Models.pdf
26
Charged Device Model Test

• Models an ESD event which occurs when a device
  acquires electrostatic charge and then touches a
  grounded object

Device discharges through ground probe
Device placed in dead-bug position
Dielectric
Field Plate
High Voltage Source
27
CDM Waveform Highly dependent on die size and
package capacitance
500V with 4pF verification module trlt400psec /
Ip14.5A / Ip2lt0.5Ip1 / Ip3lt0.25Ip1 Source
AEC-Q100-011B
28
AEC-Q100

• Automotive Electronic Council (AEC) Stress Test
  Qualification 100 AEC Q100 xxx

AEC is not a single standard but a collection of
requirements for automotive suppliers

• AEC Q100 validated suppliers have to fulfill the
  ESD regarding qualification described in it
• AEC Q100-002 HBM (JEDEC) 2000V OR AEC Q100-003
  MM (JEDEC) 200V
• AND
• AEC Q100-011 CDM (JEDEC)
• Corner Pins 750V / Non-corner pins 500V

29
Component vs. Module level tests

• ESD (pulses) testing originates from a subset of
  the wide field of EMC (Electromagnetic
  Compatibility, EMI Immunity)
• Due to the importance in the Semiconductor
  Industry, ESD testing has evolved into its own
  field of specialization

• The ESD/EMC world in general can be divided into
  two main-fields

30
ESD Standards TestsSystem vs.
Component
Goal UNDISTURBED functionality during and after
ESD stress under powered / functional conditions
Goal UNDESTROYEDcomponents after ESD
stressAll specification-parameters should stay
within its limits
ESD is a part of EMC qualification Different
behavior criteria in response to ESD on system
level exists (class A to D)
ESD is a part of product qualification
Pass/fail criteria

• Just dedicated pin combinations feasible ? I/O
  vs. GND
• The reference/enemy is always earth potential
• Relative measure of robustness of end product
  during operation

• All pin combinations can occur and are tested
• Relative measure of robustness during
  handling/manufacturing

31
ESD Test methods (Models) System vs.
Component
Module/System Level
Component Level
Human Body Model (HBM) 100pF / 1500 ? JEDEC-Norm
JESD22-A114-B (MIL-STD883D, method 3015)
Human Body Model (HBM) 150pF / 330 ? EN
61000-4-2 (so called GUN Test)
Machine Model (MM) 200pF / 0 ? JEDEC-Norm
JESD22-A115-A (correlates to HBM)
Human Body Model (HBM) 150pF / 2000 ? ISO 10605
Charged Device Model (CDM) Package pF / 0
? JEDEC-Norm JESD22-C101-A
Human Body Model (HBM) 330pF / 2000 ? ISO 10605
32
ESD Models Human Body Model ? Component Test

• A Pin-to-Pin ESD Tester (like HBM, MM Testers)
  consists of the HV source and the model with its
  values, connected to two Terminals
• The Terminals are not changed for polarity
  reversal ? The capacitance is charged one time
  positively and one time negatively?
  Tester-Ground along with parasitics stay constant

33
ESD Models Human Body Model ? Component Test

• 2 different Pin-Combination-Types are tested
• Supply-Pin-Tests
• All Pins (individually one at a time) at Terminal
  A vs. Supply-X at Terminal B
• Repeat for Supply-Y, Supply-Z, etc. at Terminal B
• Non-Supply-Pin-Test
• All Non-Supplies (individually one at a time) at
  Terminal A vs. all other non-supplies together at
  Terminal B
• Repeat for each non-supply at Terminal A
• 1 positive and 1 negative pulse for each
  pin-combination
• Step-Stress, 500V, 1kV, 2kV and 4kV should be
  used different levels and steps can be defined
• A new set of 3 devices per level is used

ESD Product Qualification Test _at_ IFX according to
JEDEC EIA/JESD 22-A114-B 2 described in IFX
Procedure 1
34
ESD Supply-Pin Test HBM ESD Each pin vs.
Supply-1 (GND)

• ESD Test P1.1
• All pins vs. Supply 1 (in this case GND)
• In this case
• 10 different combinations
• 1 and 1- pulse for each combination
• ? 20 pulses for each voltage step

35
ESD Supply-Pin Test HBM ESD Each pin vs.
Supply-2 (VBB)

• ESD Test P1.2
• All pins vs. Supply 2 (in this case VBB)
• Then subsequently All pins vs. Supply 3 (Vdd)
• In this case
• 11 different combinations
• 1 and 1- pulse for each combination
• ? 22 pulses for each voltage step

36
ESD Non-Supply-Pin Test HBM ESD Each non-supply
vs all other non-supply

• ESD Test P2
• Each non-supply vs. All other non-supply
• One non-supply at a time on Terminal A
• All other non-supplies at Terminal B
• In this case
• 8 different combinations
• 1 and 1- pulse for each combination
• ? 16 pulses for each voltage step

37
ESD Standards Test System-Level Test

• Direct Discharge Test points of normal
  accessibility.
• The Reference-Pin at System-Level test is
  Earth and not a part of the DUT
• Indirect Discharge into couple plate Test for
  radiated disturbance immunity

38
HBM System Level Tests applied to components??

• Some Customers ask for system-level test at
  component level
• Component is not powered
• Only pins which are accessible to the outside
  world are tested
• Reference pin(s) are the component ground pin(s)
• Pass/Fail according to Component test-program
• ESD current is 5x higher at a dedicated voltage
  level compared to component ESD tests

ESD _at_ 2kV Red IEC (GUN) Blue JEDEC HBM
39
Pulse Charge Comparison

• HBM 8kV is normalized to 1

40
HBM ESDGate Shorted to Source
Very small damage area due to low energy of ESD
pulses, normally cannot be seen with naked eye
41
HBM ESDGate Shorted to Source
This device had a G-S short and you can see the
burn mark is right at the boundary region of gate
poly and source metal which is common since this
is the area of highest E field strength
Gate contact metal
Gate Polysilicon
Source contact metal
42
Can ESD Sensitive Devices in an Automobile Be
Protected?

• Electrostatic discharge sensitive components can
  be protected in an automobile
• Installation of spark gap topologies
• Establishing a predictable charge well topology
  such as capacitors

43
Decrease ESD Sensitivity with a Predictable
Charge Well Topology

• Recall our earlier equation
• Place a capacitor across the device/pin to be
  protected
• The additional external capacitor sheds the
  electrostatic discharge energy, reducing the
  voltage at the pins of the semiconductor device

44
Decrease ESD Sensitivity with a Predictable
Charge Well Topology
For most robust design, the voltage at this point
should be lowered to be less than internal ESD
structure breakdown voltage so all current/energy
is shed thru external capacitor. Please note
that there is no resistor between C_prot and IC
so high current/energy can flow into IC if
internal ESD structure breaks down and begins to
conduct current
45
Decrease ESD Sensitivity with a Predictable
Charge Well Topology

• System level/gun tests ESD voltages may need to
  be 15,000V (direct contact)
• Gun tests uses 330pf for source capacitor
• For automotive technologies having ESD structures
  with 40-45V breakdown is common

C_prot (C_gun / Vbr_ESD) V_gun
(330pF / 45V) 15kV 110nF
46
Typical internal ICESD Protection Circuits
Ground Referenced Protection
VSupply Referenced Protection
IC
VSupply
External Pin
Protected Circuit
Protected Circuit
External Pin
IC
47
ESD Summary

• Electrostatic discharge occurs when excessive
  static charge on an object builds up to a very
  high voltage (thousands of volts) and causes
  device damage during contact and subsequent
  discharge (current flow) with another object
• MOS devices with insulating SiO2 gates are
  especially susceptible to ESD damage
• Different test standards have evolved for
  component level and system level tests and
  confusion can result if these standards are not
  understood and clarified in reports and
  communication
• The very fast (HBMnsecs / CDMpsecs) ESD pulses
  have low energy and result in VERY small physical
  damage signatures

48
The ABCs of ESD, EOS, and SOA

• What is ESD
• Where does ESD come from
• MOSFET Gate susceptibility
• Test Standards
• Component level vs. module level tests
• What is EOS
• What is SOA

49
What is Electrical Over Stress (EOS)?

• Electrical Over Stress is exactly what it says.
• A device is electrically stressed over its
  specified limits in terms of voltage, current,
  and/or power/energy
• Unlike ESD events, EOS is the result of "long"
  duration stress events (millisecond duration or
  longer)
• Excessive energy from turning off inductive loads
• Load Dump
• Extended operation at junction temperatures gt
  150degC
• Repetitive excessive thermal cycling
• Excessive/extended EMC exposure, etc.
• EOS often results in large scorch marks,
  discoloration of metal, melted metallization
  and/or bond wires, and massive destruction of the
  semiconductor component

50
What is Electrical Over Stress (EOS)?

• Failures from EOS can result in the following
• Hard failure failure is immediate and results
  in a complete non-operational device
• Soft failure EOS results in a marginal failure
  or a shift in parametric performance of the
  device
• Latent failure At first the EOS results in a
  non-catastrophic damage but after a period of
  time further degradation occurs resulting in a
  hard or soft failure

51
EOS Thermal Lifetime Curve
Lifetime
Point of accelerated device qualification
10 000 h
Lifetime curve for device worst case parameters
1 000 h
100 h
270C
10 h
app. 350C
170C
1 h
Irreversible damage
Over-temperatureshutdown
220C 260C
0.1 h
Soldering
Device temperature
150C
200C
270C
350C
?
?
?
?
Spec valid, full lifetime, full function
Device destruction, irreversible
damage, permanent out of control
Spec restricted, reduced lifetime, limited
functionality
No spec, no permanent damage, highly reduced
lifetime, no function guaranteed
52
What is Electrical Over Stress (EOS)?

• What indicates EOS?

Degradation/recrystalisation of metal
(400ºC) ---also repetitive fast transientslt100ºC
Scorched/Melted metal (650ºC)
Melted silicon (1200ºC)
53
EOS Failure signature from excessive load dump
Scorched/melted metal
54
EOS Failure Signatures---Generalities

• Visualization of single- and repetitive pulse
  events

This isnt a completely black white effect, but
there can be a significant difference in single-
and repetitive pulse failure signatures
55
EOS Failure signature from excessive inductive
turn-off energy

• Example Inductive clamp single pulse
  IDS(start)10A, t11.8 ms, T25C, Vbb 12V

I_ramp(10A/11.8ms) E2.14 Joules
Failure signature (10A)- No metal degradation-
Scorch in DMOS field- NO bond fuse
EOS at the hot spot
No metal degradationnear bond
56
EOS Failure signature from repetitive thermal
cycling combined with high current
Severely degraded recrystalized metal
57
Electrical Over Stress (EOS)

• A common failure for electrical over stresses is
• MELTED METALLIZATION AND/OR BOND WIRES

Gold Wire DC Ratings
Aluminum Wire DC Ratings
350?m 40A
50?m 2.5A
25?m 1A
50?m 2A
125?m 8A
Assumes TJ lt 150C, TLeads lt 85C, TWire lt 220C,
and Wire Lengthlt3mm
58
How to Electrically Over Stress Components

• Put components in/out of sockets while power
  already applied (hot plug)
• Applying electrical signals which exceeds a
  components ratings
• Apply an input signal to a device before applying
  supply voltage and/or ground
• Apply an input signal to a device output
• Use an inexpensive power supply (supply
  overshoot)
• Provide insufficient noise filtering on the
  boards input line(s)
• Use a poor ground with high resistance and
  inductance

59
EOS Summary

• Electrical over stress refers to a condition when
  a device is electrically stressed over its
  specified limits
• EOS often catastrophically damages devices by
  degrading or melting of metallization and bond
  wires
• Operation of devices within the specified Safe
  Operating Area will eliminate electrical over
  stress damage

60
The ABCs of ESD, EOS, and SOA

• What is ESD
• Where does ESD come from
• MOSFET Gate susceptibility
• Test Standards
• Component level vs. module level tests
• What is EOS
• What is SOA

61
Safe Operating Area (SOA)

• The safe operating area is a set of conditions
  specified for a certain device
• Within the safe operating area, the semiconductor
  component is specified to operate as expected
• By definition, no electrical over stress occurs
  within the specified safe operating area

62
SOA Graph for MOS Transistor

• Single pulse, Tcase 25C, Tjunction lt 125C

63
SOA Graph forLinear Voltage Regulator

• VOUT 5V, Tjunction lt 150C

Soldered to board with 3cm2 copper heatsink
Ta 25C
Ta 85C
Ta 125C
64
The ABCs of ESD, EOS, and SOA
65
Thank you!

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