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Whats the Next Big Thing in Simulation-Based
Verification?
William H. Joyner, Jr. Semiconductor Research
Corporation San Francisco, California November
14, 2003
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True or False Formal Methods and Simulation

• Formal methods are not applicable in the real
  world
• Formal methods can be used only by experts
• Simulation has been (and will be) the most
  important verification technique
• Formal methods and simulation work hand in hand
  to solve real world verification problems
• Simulation is a dirty word in academic
  publications
• Simulation is a mature technology
• Funding tends toward exotic, formal techniques
• Correct by Construction techniques will make
  verification unnecessary

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Recent Conferences

• DAC 2003
• Simulation Coverage and Generation for
  Verification
• Testbench, Verification and Debugging Practical
  Considerations
• SAT and BDD Algorithms for Verification Tools
• Advances in SAT
• Panel Formal Verification Prove It or Pitch It!
• ICCAD 2003
• Emerging Techniques in Dynamic Verification
• Automatic Abstraction for Formal Verification
• Optimizations for Verification Engines
• Simulation at the Nanometer Scale
• Tutorial Recent Advances in Formal Verification

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2003 ITRS

• Verification has become the dominant cost in the
  design process. On current projects,
  verification engineers outnumber designers, with
  this ratio reaching two or three to one for the
  most complex designs. Design conception and
  implementation are becoming mere preludes to the
  main activity of verification.
• Without major breakthroughs, verification will
  be a non-scalable, show-stopping barrier to
  further progress in the semiconductor industry.
• The overall trend from which these breakthroughs
  will emerge is the shift from ad hoc verification
  methods to more formal ones. Whether any
  particular formal verification technique will
  succeed is debatable, but the overall shift is
  unavoidable. One should not attempt to verify
  the functionality of a system design by
  repeatedly building models, simulating them on an
  ad hoc selection of vectors, and then patching
  any bugs that happen to be noticed but this is
  exactly the methodology used today. A
  trial-and-error verification methodology based on
  simulation is inherently slow and unscalable.

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2003 ITRS
Conventional simulation can provide high
coverage of a small design, or extremely poor
coverage of a large design, but not high coverage
of a large design.
Formal verification provides complete coverage
of the possible behaviors of the design being
verified, but cannot currently handle large
designs. Semi-formal verification attempts to
blend formal and simulation-based techniques,
sacrificing coverage to gain capacity. The
challenge is to move toward the upper right
corner of the diagram.
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SRC Funding of Verification
More money in 2004 than 2003 Money migrating
from process and device technology to design and
tools More projects moving to system level -
Still less than in 2001
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Words

• Words found in current research in formal
  verification
• Hybrid, test cases, capacity, counterexample,
  usability, practical, coverage
• Words found in current research in dynamic
  verification
• Bayesian, data mining, solver, ATPG, modeling,
  constraints, SAT, genetic algorithms
• The Next Big Thing in Simulation-Based
  Verification A combination of formal methods,
  smart simulation, smart coverage analysis,
  hardware acceleration, all raised to the system
  level, encompassing the circuit and lower levels,
  and extended to analog, mixed signal, MEMS, etc.

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Quotes

• E. W. Dijkstra, 1972, The Humble Programmer
• Program testing can be a very effective way to
  show the presence of bugs, but it is hopelessly
  inadequate for showing their absence.
• The only effective way to raise the confidence
  level of a program significantly is to give a
  convincing proof of its correctness
• D. E. Knuth, 1977
• Beware of bugs in the above code I have only
  proved it correct, not tried it.

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Quotes

• Dan Beece, 2003
• People who work in formal verification methods
  are smart, and it's good to have smart people
  working on a project.
• Carl Pixley, 2003
• Only FV can give 100 confidence.
• George McGovern, 1972
• I am 1,000 percent for Tom Eagleton and I have
  no intention of dropping him from the ticket.
• Brian Bailey, 2003
• Formal verification will be an integral part
  of the dynamic verification methodology.