LECTURE 2 DIGITAL ELECTRONICS

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LECTURE 2 DIGITAL ELECTRONICS
Dr Richard ReillyDept. of Electronic
Electrical EngineeringRoom 153, Engineering
Building
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Digital Logic Families

• Gates perform one or more operations.
• simply electronic circuits composed of resistors,
  diodes and transistors
• Originally gates were composed just from
  resistors and diodes, due to expense of
  transistors.
• Due to fabrication procedures, all gates are now
  constructed exclusively from transistors.
• The style in which transistors are connected
  characterises each logic family or library and
  gives it its unique name.

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DIGITAL LOGIC FAMILIES

•     Diode-Resistor Logic (DRL)
•     Diode-Transistor Logic (DTL)
•     Resistor-Transistor Logic (RTL)
•  
•     Transistor-Transistor (TTL)
•     standard TTL
•     Schottky-Clamped TTL
•     Low-Power Schottky-Clamped TTL
•     Advanced Schottky-Clamped TTL
•  
•     Emitter-Coupled Logic (ECL)
•     ECL 10K Series
•     ECL 100K Series

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DIGITAL LOGIC FAMILIES

•     Integrated Injection Logic (I2L)
•     standard I2L
•     Schottky I2L
•     Schottky Transistor I2L
•  
•     NMOS
•  
•     CMOS Logic
•     standard CMOS
•     4000 Series CMOS Logic Family
•     4000B and 74C Series
•     74HC/HCT Series
•     74AC/ACT Series
•     BiCMOS

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Metrics for Logic Gate Comparison

• How do you compare these different logic families
  ?
• Comparison on the application ?
• Comparison on the cost ?
• Any other ?

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Metrics for Logic Gate Comparison

• Before a discussion of the basic logic families,
  several metrics must be defined to allow
  comparison of different families.

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Metrics for Comparing Logic Families

• Logic Level
• Noise Margin
• Fan out
• Power Dissipation
• Propagation Delay

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METRIC 1 Logic Levels

• Circuit behaviour explained very well in terms of
  voltage levels measured in volts (V)
• but not necessarily in terms of Boolean values 0
  and 1.
•  
• To accommodate these Boolean values, gate
  circuits are designed in such a way that only two
  voltage levels, high (H) and low (L) are
  observable in steady state at gate inputs and
  outputs.
•  
• Thus a mapping exists from 0 and 1 to voltage
  levels H and L.
• Mapping can be accomplished in two different ways
• Results in two different logic systems
• positive and negative.

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Logic Levels

• Example
• The gate circuit whose output is L only when both
  inputs are H
• Performs the NAND operation in positive logic
• Performs the NOR operation in negative logic
•  
• Similarly gate circuit whose output is L only
  whenever one input is H
• Performs the NOR operation in positive logic
• Performs the NAND operation in negative logic

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New Symbol

• To distinguish between positive and negative
  logic
• a small triangle as a polarity indicator for
  negative logic in any input and output signal
  line.
• Negative logic NAND (positive logic NOR)
• The mixing of logic levels was practised
  frequently in the past when designers mixed gates
  from different logic families on the same board.
• Since the mid-eighties or so, all new ICs have
  been made with the CMOS logic family, which uses
  positive logic.
• Negative logic has fallen out of fashion.

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Noise Margin
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METRIC 2 Noise Margins

• Gate circuits are constructed to sustain
  variations in input and output voltage levels.
• variations are usually result of several
  different factors.
•  
• Batteries lose their full potential, causing the
  supply voltage to drop
• High operating temperatures may cause a drift in
  transistor voltage and current characteristics
• Spurious pulses may be introduced on signal lines
  by normal surges of current in neighbouring
  supply lines.

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Noise Margins

• All these undesirable voltage variations that are
  superimposed on normal operating voltage levels
  are called noise.
•  
• All gates designed to tolerate a certain amount
  of noise on their input and output ports.
• The maximum noise voltage level that is tolerated
  by a gate is called a noise margin.
•  
•  
• Noise margin derived from I/PO/P voltage
  characteristic
• Measured under different operating conditions
• Normally supplied in documentation about gate
  from manufacturer.

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Noise Margins

• Typical input/output voltage characteristic for
  (TTL) family
• the output voltage is plotted as a function of
  the input voltage.

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Noise Margins

• The input/output voltage characteristic drifts
  under different operating conditions also show
  the drifting range by the shaded area.
•  
•  
• From the figure we can see that the given gate
  operates in 3 different modes
• High output
• Transition
• Low output

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Noise Margins

• High Mode
• When VI is between 0 and 0.8 V
• the output voltage VO is greater than 2.4 V
• and
• less than the supply voltage VCC, which is
  usually 5.0 V.
• i.e 2.4V lt VO lt 5.0V
•  
• Transition Mode
• When VI is between 0.8 and 2.0 V
•     the gates switches from H to L

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Noise Margins

• Low Mode
• When VI is greater than 2.0 V
•     the output voltage VO is greater than 0 V
• and
•     less than 0.4 V.
• i.e 0V lt VO lt 0.4V

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How to determine noise margins?

• Compare input and output voltage ranges of gates
  in same family.
•  
• output voltage range of a driving gate on LHS
  input voltage range of the driven gate on RHS
•  Any voltage between VOH and VCC is considered H.
• any voltage between 0 and VOL is considered L.

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How to determine noise margins?

• Similarly
• Any voltage between VIH and VCC is considered H
• Any voltage between 0 and VIL is considered L
• The voltage difference VOH - VIH called
  high-level noise margin
• Any noise voltage smaller than VOH - VIH will be
  tolerated and will not change the output value of
  the driven gate.
• For the same reason, the voltage difference VIL -
  VOL is called the low-level noise margin.

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How to determine noise margins?

• In the example of transistor-transistor logic
  (TTL)
• VOH 2.4 V
• VIH 2.0 V
• VIL 0.8 V
• VOL 0.4 V
•  
• Thus both high and low level noise margins are
  0.4 V.
• Thus any noise smaller than 0.4 V will not
  disturb gate operation.
• Such high noise margins, which are not available
  in analog circuits, make digital designs superior
  to analog.

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Fan-Out
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METRIC 3 Fan-out

• To date have understood that each gate can drive
  several other gates.
•  
• The number of gates that each gate can drive,
  while providing voltage levels in the guaranteed
  range is called the standard load or fan-out.
•  
• The fan-out really depends on the amount of
  electric current a gate can source or sink while
  driving other gates.

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Fan-out

• When the gate output is H
• Gate behaves as a current source since IOH flows
  out of the driver gate and into the set of driven
  gates.
• The current IOH equals the sum of all input
  currents indicated by IIH, flowing into the
  driven gates.

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Fan-out

• When the gate output is L
• Gate behaves as a current sink since IOL flows
  into the gate and out of the driven gates.
• The current IOL is again equal to the sum of all
  input currents IIL, flowing out of all the driven
  gates.

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Fan-out

• Since all gates in a logic family are constructed
  in such a way that each gate requires the same
  IIH and the same IIL,
• can compute fan-out in the following way

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Fan-out

• Example
• Input and output current for the
  transistor-transistor logic (TTL) family are the
  following
•  
• IOH 400 ?A
• IOL 16 ?A
• IIH 40 ?A
• IIL 1.6 ?A
•  
• Therefore the fan-out is ?

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Fan-out

• This means that each gate can drive 10 other
  gates in the same family
• without getting out of its guaranteed range of
  operation.
•  
• In cases where more than 10 gates are connected
  to the output of a single gate of this family,
  the output voltage levels will degrade and the
  gate will slow down.
• Modern MOS logic families have a fan-out of about
  50,
• since each gate must source or sink a current
  only during the transition from H to L or L to H.

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Power Dissipation
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Metric 4 Power Dissipation

• Each gate is connected to a power supply VCC
• Draws a certain amount of current during its
  operation.
•  
• Since each gate can be in a High state,
  Transition or Low state.
• can distinguish 3 different currents drawn from
  power supply.
• ICCH
• ICCT
• ICCL

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TTL

• In some older logic families, such as TTL, the
  transition current ICCT is negligible
• in comparison to ICCH and ICCL.
•  
• Assuming that gate spends an approximately equal
  amount of time in the high and the low states and
  approximately no time in the transition state
• ?
• Thus the average power dissipation (product of
  average current and power supply voltage)
• Power dissipation is measured in mW
• for the TTL family 10mW

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CMOS

• In more modern technologies such as the CMOS
  family
• the steady-state currents ICCH and ICCL are
  negligible in comparison with ICCT.
• Since ICCT is relatively small the typical power
  dissipation of CMOS gates is small.
• But the power dissipation increases with the
  frequency with which the gate output is changing

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Power Dissipation

• Power Dissipation is an important metric for two
  reasons.
•  
• Amount of current and power available in a
  battery is nearly constant.
• power dissipation of a circuit or system defines
  battery life.
• The greater the power dissipation, the shorter
  the battery life.
•  
•  
• Power dissipation is proportional to the heat
  generated by the chip or system.
• Excessive heat dissipation may increase operating
  temperature and cause gate circuitry to drift out
  of its normal operating range
• will cause gates to generate improper output
  values.
• Thus power dissipation of any gate implementation
  must be kept as low as possible

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Propagation Delay
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Metric 5 Propagation Delay

• Propagation delay defined as
•  
• Average time needed for an input change to
  propagate to the output
• Typically nanoseconds.
• The propagation delay can be obtained from gate
  input and output waveforms.

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Propagation Delay

• Input and consequently output signal do not
  switch their values instantly
• H ? L and L ? H changes can be delayed for
  different amounts of time
•  
•  
• Since the signal values do not change instantly,
  define rise time
• delay for a signal to switch from 10 to 90 of
  its nominal value.
•  
• Similarly define the fall time.
• delay for a signal to switch from 90 to 10 of
  its nominal value.

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Propagation Delay

• Since H ? L and L ? H transitions are not delayed
  equally, can define
•   tPHL H ? L propagation delay
• tPLH L ? H propagation delay
•  
• tPHL is defined as
• time necessary for output signal to reach 50 of
  its nominal value on H ? L transition after input
  signal reached 50 of its nominal value.
• tPLH is defined similarly.
•   
• Propagation delay tP defined as average value of
  tPHL and tPHL.

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Propagation Delay

• 2-input NAND in the TTL family
• tPHL 7 nsec
• tPLH 11 nsec ? tp 9 nsec (711/2)
•  
• 2-input NAND in the CMOS family tp 1 nsec
•  
•  
• As manufacturers cannot guarantee the same
  nominal value on every gate they fabricate
• Usually give the maximum delay values (not that
  interested in the minimum delay)
• no gate will exceed this maximal value.
•   
• 2-input NAND in the TTL family, the maximal
  propagation delays
• tPHL 22 nsec
• tPLH 15 nsec ? tp 18.5 nsec (2215/2)

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Summary

• Need to have metrics to allow Digital Designers
  compare different designs.
• So either the cost effective or fastest design
  can be implemented for each application.

• Lecture tonight