3 BitCell BackGated, NVM FET

1
3 Bit/Cell Back-Gated, NVM FET

• A. Padilla
• Acknowledgements
• n/a

2
Motivation / Goals

• Motivations
• Double-gated, thin-body FETs are most scalable
• Back-gated FD-SOI FETs are easier to manufacture
  than double-gated (i.e., FinFET) structures.
• Back-gated FETs may occupy a smaller layout area
  than a 3D structure.

Back-Gated FET
Double-Gated FET

• Goal
• Develop the Technology of a Multi-bit-per-cell,
  Back-Gated FET Structure.

3
Approach

• Demonstrate concept through Simulations
• Basic Idea
• Use symmetry of cell, independent-gate biasing to
  independently read or modify the information
  stored within (each bit of the) cell.
• Use DVT to distinguish charge storage
  independently on every bit.
• Program bit1 via FN Tunneling Program bit 2 (or
  3) via HEI or BTBEI.
• Proposed (Virtual GND in SOI) architecture
  shown below

4
Key Results to Date

• Successful READ of each bit

//Read bit _at_ FG (bit1)
//Read bit _at_ BG (bit2 or bit3)

• gt3 orders of magnitude in separation can be
  achieved with these settings.

5
Plans / Milestones

• Define a Process Flow for proposed NOR-type
  Architecture
• File Invention Disclosure
• Fabricate, test prototype cell
• Publish Results (if applicable)
• Fabricate, test mini-array architecture (should
  prior results be successful).