CMOS Manufacturing Process

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CMOSManufacturingProcess
2
CMOS Process
3
CMOS Inverter Layout
4
Patterning on Si
5
Semiconductor fabrication (1)
2
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Semiconductor Fabrication (2)
1
3
4
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Semiconductor Fabrication (3)
3
3
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Semiconductor Fabrication (4)
4
END
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Circuit Under Design
This two-inverter circuit (of Figure 3.25 in the
text) will be
manufactured in a twin-well process.
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Circuit Layout
Vdd
B4
B2
pMOS-1
S2
S4
pMOS-2
Inverter 1 nMOS-1 pMOS-1 Inverter
2 nMOS-2 pMOS-2
G2
G4
IN2OUT1
D4
D2
IN1
OUT2
OUT1
IN2
Inverter 2
Inverter 1
D3
D1
G3
G1
S3
S1
nMOS-2
GND
B3
B1
nMOS-1
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Start Material
A
pMOS
nMOS
A
A
A
Cross-sections will be shown along vertical
line A-A
Si n-type
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N-well Construction
pMOS
(1) Oxidize wafer
(2) Deposit silicon nitride
nMOS
(3) Deposit photoresist
photoresist
Si n-type
silicon nitride silicon dioxide
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N-well Construction
pMOS
(4) Expose resist using n-well mask
nMOS
Exposed resist
Si n type
14
N-well Construction
pMOS
(5) Develop resist
nMOS
(6) Etch nitride and
(7) Grow thick oxide
Si n type
15
N-well Construction
pMOS
(8) Implant n-dopants (phosphorus)
nMOS
m
(up to 1.5
m deep)
thick oxide
n-well
Si n type
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P-well Construction
pMOS
Repeat previous steps
nMOS
pMOS
nMOS
n-well
p-well
Si n type
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Grow Gate Oxide
pMOS
nMOS
Gate oxide 55 nm thin
pMOS
nMOS
n-well
p-well
Si n type
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Grow Thick Field Oxide
pMOS
Field Oxide 0.9 mm thick
nMOS
Uses Active Area mask
pMOS
nMOS
Is followed by threshold-adjusting implants
n-well
p-well
Si n type
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Polysilicon layer
pMOS
Polysilicon Deposition
nMOS
pMOS
nMOS
n-well
p-well
Si n type
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Source-Drain Implants
pMOS
photoresist
nMOS
pMOS
nMOS
n-well
p-well
Si n type
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Source-Drain Implants
pMOS
nMOS
pMOS
nMOS
S
G
B
D
B
G
S
D
n-well
p-well
Si n type
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Contact-Hole Definition
(1) Deposit inter-level Dielectric (SiO2) 0.75
mm
pMOS
(2) Define contact opening using contact mask
nMOS
pMOS
nMOS
n-well
p-well
Si n type
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Aluminum-1 Layer
pMOS
Aluminum evaporated (0.8 mm thick)
OUT
IN
nMOS
followed by other metal layers and glass
Vdd
GND
IN
S
B
OUT
G
B
D
G
S
D
G
pMOS
nMOS
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Advanced Metalization
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Intel 0.09 ?m Generation
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Downsizing MOSFET below 0.1 ?m
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Design Rules
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Design Rules

• Interface between designer and process engineer
• Guidelines for constructing process masks
• Unit dimension Minimum line width
• scalable design rules lambda parameter
• absolute dimensions (micron rules)

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CMOS Process Layers
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Intra-Layer Design Rules
4
Metal2
3
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Transistor Layout
Transistor
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Vias and Contacts
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Select Layer