DFT Technologies for HighQuality LowCost Manufacturing Tests

1
DFT Technologies for High-Quality Low-Cost
Manufacturing Tests

• Yuval Snir
• Advanced Digital design flow seminar 2006

2
Agenda

• Background facing with new era of defects
• Concepts Models
• Problem Regards testing with low cost
• fast technologies
• Main goal Two effective implementation
• solutions

3
Background

• The Shrinkage of semiconductor devices brought a
  new distribution of defects
• Old methods such as the stuck-at-fault-model and
  standard memory BIST are no longer adequate.
• Timing defects have become more significant (at
  least 2 of all defects)
• Need higher quality tests for reducing the
  defective chips (DPM)

4
Background

• For 130 nm fabrication
• Of yield 70
• No statistical faults
• Defect rate will be 0.7
• 7000 defective devices
• un detected per million
• (DPM)

5
Concepts Models

• ATPG Automatic Test-Pattern Generation
• On die hardware tool that generates patterns for
  false detection.
• Test-Patterns Behavior of output as a function
• Of the inputs
• Scan Chains vectors of inputs/outputs

6
Concepts Models

• Stuck-at fault-model
• the most popular fault model used in practice
• a line whose status is stuck at a given value
  (normally 0 or 1).
• Input 1,1 reveals S_at_0
• fault

7
Concepts Models

• At-speed fault model
• Test for timing faults
• most companies use this test today
• Check the duration in which a logic gate Change
  its output
• Check whether a circuit behave as expected at the
  right speed typically high clock frequencies
• The most common detection is the broadside
  transition pattern which checks for slow-to-rise
  slow-to-fall faults.
• Broadside patterns involve loading scan cells to
  produce both an initial value and an opposite
  value ready to propagate through the path.

8
Concepts Models

• At-speed fault model
• Example
• Initialization
• B1
• Opposite value
• Propagates from
• B to C

capture
launch
9
Concepts Models

• At-speed fault model
• Two possibilities to
• Perform the at-speed
• test

broadside
launch of shift
10
The Problem

• Desired fast low cost technologies tests
• Transition pattern set is 3-5 bigger then
• stuck-at pattern set
• Sometimes there isnt enough room on the tester
  memory for both pattern sets.
• Yields expensive tester reloads of the memory.

11
solutions

• 1. Effective Merging At-Speed with Stuck-At
  Patterns
• 2. EDT Embedded Deterministic Test

12
Merging At-Speed with Stuck-At Patterns Sets

• The TDF (Transition delay fault) patterns also
  detect a significant percentage of stuck-at
  faults
• Truncate TDF patterns

13
Merging Patterns - Case Study

Design demands
Characteristic of the design

• The tester can hold up to 10,000 test pattern
• The highest priority best possible coverage for
  stack_at_
• One TDF pattern set for each clock domain and one
• For cross clock domain.

14
Merging Patterns - Case Study

Test generation results before optimization

• Due to the typically slow operation of the tester
• The TDF test coverage is only 85.14.
  

15
Merging Patterns - Case Study

Test generation results before truncation
optimization
16
Merging Patterns - Case Study

• Flow for generating higher coverage
• Arrange TDF test patterns from most significant
  to least
• Truncate TDF patterns ( 90 of the overall
  achievable)
• Fault grade the truncated TDF patterns for SAF
• Generate top-off SAF pattern set

17
Merging Patterns - Case Study

Test generation results after truncation
optimization
18
Merging Patterns - Case Study

Test generation methodology comparison
19
Review -The Problem

• Utilize tester memory!

20
EDT-Embedded deterministic test

An Embedded deterministic test architecture
21
EDT-Embedded deterministic test

• Minimize test time and utilize memory
• Uses embedded compression logic
• Enables scan chains to increase by up to 100x
• Not necessitate special design
• Bypass-Test generation can be done also in ATPG

22
EDT-How this is work?

• With ATPG 1-5 of scan cells get specified.
• With EDT there is a compression of specified
  cells

23

• I have to go now